Datasheet Texas Instruments SN74LVT8980ADWRG4 — Ficha de datos
Fabricante | Texas Instruments |
Serie | SN74LVT8980A |
Numero de parte | SN74LVT8980ADWRG4 |
Controladores de bus de prueba integrados IEEE STD 1149.1 (JTAG) TAP Masters con interfaces de host genéricas de 8 bits 24-SOIC -40 a 85
Hojas de datos
SN54LVT8980A, SN74LVT8980A datasheet
PDF, 865 Kb, Revisión: B, Archivo publicado: marzo 18, 2004
Extracto del documento
Precios
Estado
Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
Disponibilidad de muestra del fabricante | No |
Embalaje
Pin | 24 |
Package Type | DW |
Industry STD Term | SOIC |
JEDEC Code | R-PDSO-G |
Package QTY | 2000 |
Carrier | LARGE T&R |
Device Marking | LVT8980A |
Width (mm) | 7.5 |
Length (mm) | 15.4 |
Thickness (mm) | 2.35 |
Pitch (mm) | 1.27 |
Max Height (mm) | 2.65 |
Mechanical Data | Descargar |
Paramétricos
Bits | 8 |
Operating Temperature Range | -40 to 85 C |
Output Drive (IOL/IOH)(Max) | 64/-32 mA |
Package Group | SOIC |
Package Size: mm2:W x L | 24SOIC: 160 mm2: 10.3 x 15.5(SOIC) PKG |
Rating | Catalog |
Technology Family | LVT |
VCC(Max) | 3.6 V |
VCC(Min) | 2.7 V |
tpd @ Nom Voltage(Max) | 30 ns |
Plan ecológico
RoHS | Obediente |
Notas de aplicación
- Programming CPLDs Via the 'LVT8986 LASPPDF, 819 Kb, Archivo publicado: nov 1, 2005
This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to - LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, Archivo publicado: dic 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
Linea modelo
Serie: SN74LVT8980A (3)
- SN74LVT8980ADW SN74LVT8980ADWR SN74LVT8980ADWRG4
Clasificación del fabricante
- Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic