Datasheet Texas Instruments SN74LVT573DW — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | SN74LVT573 |
| Numero de parte | SN74LVT573DW |
3.3-V ABT Octal Cierres transparentes tipo D con salidas de 3 estados 20-SOIC -40 a 85
Hojas de datos
3.3-V ABT Octal Transparent D-Type Latches datasheet
PDF, 1.1 Mb, Revisión: D, Archivo publicado: jul 1, 1995
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | NRND (No recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 20 |
| Package Type | DW |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 25 |
| Carrier | TUBE |
| Device Marking | LVT573 |
| Width (mm) | 7.5 |
| Length (mm) | 12.8 |
| Thickness (mm) | 2.35 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 2.65 |
| Mechanical Data | Descargar |
Reemplazos
| Replacement | SN74LVTH573DW |
| Replacement Code | Q |
Plan ecológico
| RoHS | Obediente |
Notas de aplicación
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, Archivo publicado: dic 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
Linea modelo
Serie: SN74LVT573 (2)
- SN74LVT573DW SN74LVT573PWR
Clasificación del fabricante
- Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Latch