Datasheet Texas Instruments SN74HC112NE4 — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | SN74HC112 |
| Numero de parte | SN74HC112NE4 |
Chanclas de doble JK de borde negativo disparado con 16-PDIP claro y preestablecido -40 a 85
Hojas de datos
SN54HC112, SN74HC112 datasheet
PDF, 598 Kb, Revisión: F, Archivo publicado: sept 26, 2003
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 16 |
| Package Type | N |
| Industry STD Term | PDIP |
| JEDEC Code | R-PDIP-T |
| Package QTY | 25 |
| Carrier | TUBE |
| Device Marking | SN74HC112N |
| Width (mm) | 6.35 |
| Length (mm) | 19.3 |
| Thickness (mm) | 3.9 |
| Pitch (mm) | 2.54 |
| Max Height (mm) | 5.08 |
| Mechanical Data | Descargar |
Paramétricos
| Bits | 2 |
| F @ Nom Voltage(Max) | 70 Mhz |
| ICC @ Nom Voltage(Max) | 0.04 mA |
| Output Drive (IOL/IOH)(Max) | -4/4 mA |
| Package Group | PDIP |
| Package Size: mm2:W x L | See datasheet (PDIP) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | HC |
| VCC(Max) | 6 V |
| VCC(Min) | 2 V |
| Voltage(Nom) | 3.3,5 V |
| tpd @ Nom Voltage(Max) | 41 ns |
Plan ecológico
| RoHS | Obediente |
| Pb gratis | Sí |
Notas de aplicación
- HCMOS Design Considerations (Rev. A)PDF, 207 Kb, Revisión: A, Archivo publicado: sept 9, 2002
This document describes a potential problem designers may encounter when using high-speed CMOS (HC) logic devices. There also is a broad range of CMOS-system to non-CMOS-system interfaces that need to be considered. The design engineer inevitably encounters these interfaces. Key considerations for handling these interfaces are also discussed in this book.
Linea modelo
Serie: SN74HC112 (9)
Clasificación del fabricante
- Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop