Datasheet Texas Instruments SN74AVC20T245 — Ficha de datos

FabricanteTexas Instruments
SerieSN74AVC20T245
Datasheet Texas Instruments SN74AVC20T245

Transceptor de bus de suministro dual de 20 bits con traducción de voltaje configurable y salidas de 3 estados

Hojas de datos

SN74AVC20T245 20-Bit Dual-Supply Bus Transceiver datasheet
PDF, 1.3 Mb, Revisión: F, Archivo publicado: abr 19, 2005
Extracto del documento

Precios

Estado

74AVC20T245DGGRG474AVC20T245DGVRG4SN74AVC20T245DGGSN74AVC20T245DGGRSN74AVC20T245DGVRSN74AVC20T245ZQLR
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

74AVC20T245DGGRG474AVC20T245DGVRG4SN74AVC20T245DGGSN74AVC20T245DGGRSN74AVC20T245DGVRSN74AVC20T245ZQLR
N123456
Pin565656565656
Package TypeDGGDGVDGGDGGDGVZQL
Industry STD TermTSSOPTVSOPTSSOPTSSOPTVSOPBGA MICROSTAR JUNIOR
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PBGA-N
Package QTY2000200035200020001000
CarrierLARGE T&RLARGE T&RTUBELARGE T&RLARGE T&RLARGE T&R
Device MarkingAVC20T245WG245AVC20T245AVC20T245WG245WG245
Width (mm)6.14.46.16.14.44.5
Length (mm)1411.3141411.37
Thickness (mm)1.151.051.151.151.05.75
Pitch (mm).5.4.5.5.4.65
Max Height (mm)1.21.21.21.21.21
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargar

Paramétricos

Parameters / Models74AVC20T245DGGRG4
74AVC20T245DGGRG4
74AVC20T245DGVRG4
74AVC20T245DGVRG4
SN74AVC20T245DGG
SN74AVC20T245DGG
SN74AVC20T245DGGR
SN74AVC20T245DGGR
SN74AVC20T245DGVR
SN74AVC20T245DGVR
SN74AVC20T245ZQLR
SN74AVC20T245ZQLR
Bits202020202020
F @ Nom Voltage(Max), Mhz100100100100100100
ICC @ Nom Voltage(Max), mA0.0650.0650.0650.0650.0650.065
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Package GroupTSSOPTVSOPTSSOPTSSOPTVSOPBGA MICROSTAR JUNIOR
Package Size: mm2:W x L, PKG56TSSOP: 113 mm2: 8.1 x 14(TSSOP)56TVSOP: 72 mm2: 6.4 x 11.3(TVSOP)56TSSOP: 113 mm2: 8.1 x 14(TSSOP)56TSSOP: 113 mm2: 8.1 x 14(TSSOP)56TVSOP: 72 mm2: 6.4 x 11.3(TVSOP)56BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)
RatingCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNo
Technology FamilyAVCAVCAVCAVCAVCAVC
VCC(Max), V3.63.63.63.63.63.6
VCC(Min), V1.21.21.21.21.21.2
Voltage(Nom), V1.2,1.5,1.8,2.5,3.31.2,1.5,1.8,2.5,3.31.2,1.5,1.8,2.5,3.31.2,1.5,1.8,2.5,3.31.2,1.5,1.8,2.5,3.31.2,1.5,1.8,2.5,3.3
tpd @ Nom Voltage(Max), ns3.8,3.63.5,3.43.8,3.63.5,3.43.8,3.63.5,3.43.8,3.63.5,3.43.8,3.63.5,3.43.8,3.63.5,3.4

Plan ecológico

74AVC20T245DGGRG474AVC20T245DGVRG4SN74AVC20T245DGGSN74AVC20T245DGGRSN74AVC20T245DGVRSN74AVC20T245ZQLR
RoHSObedienteObedienteObedienteObedienteObedienteObediente

Notas de aplicación

  • Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B)
    PDF, 126 Kb, Revisión: B, Archivo publicado: jul 7, 1999
    Texas Instruments (TI[TM]) next-generation logic is called the Advanced Very-low-voltage CMOS (AVC) family. The AVCfamily features TI?s Dynamic Output Control (DOC[TM]) circuit (patent pending). DOC circuitry automatically lowers the outputimpedance of the circuit at the beginning of a signal transition, providing enough current to achieve high signaling speeds, thensubsequently raises the i
  • AVC Logic Family Technology and Applications (Rev. A)
    PDF, 148 Kb, Revisión: A, Archivo publicado: agosto 26, 1998
    Texas Instruments (TI?) announces the industry?s first logic family to achieve maximum propagation delays of less than 2 ns at 2.5 V. TI?s next-generation logic is the Advanced Very-low-voltage CMOS (AVC) family. Although optimized for 2.5-V systems, AVC logic supports mixed-voltage systems because it is compatible with 3.3-V and 1.8-V devices. The AVC family features TI?s Dynamic Output Control (
  • Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)
    PDF, 390 Kb, Revisión: B, Archivo publicado: abr 30, 2015
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revisión: B, Archivo publicado: mayo 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Selecting the Right Level Translation Solution (Rev. A)
    PDF, 313 Kb, Revisión: A, Archivo publicado: jun 22, 2004
    Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati

Linea modelo

Clasificación del fabricante

  • Semiconductors> Logic> Voltage Level Translation> Direction Controlled Voltage Translation