Datasheet Texas Instruments SN74AS280 — Ficha de datos
Fabricante | Texas Instruments |
Serie | SN74AS280 |
Generadores / verificadores de paridad de 9 bits
Hojas de datos
9-Bit Parity Generators/Checkers datasheet
PDF, 807 Kb, Revisión: C, Archivo publicado: dic 1, 1994
Extracto del documento
Precios
Estado
SN74AS280D | SN74AS280N | SN74AS280N3 | SN74AS280NSR | |
---|---|---|---|---|
Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Obsoleto (El fabricante ha interrumpido la producción del dispositivo) | Activo (Recomendado para nuevos diseños) |
Disponibilidad de muestra del fabricante | No | No | No | No |
Embalaje
SN74AS280D | SN74AS280N | SN74AS280N3 | SN74AS280NSR | |
---|---|---|---|---|
N | 1 | 2 | 3 | 4 |
Pin | 14 | 14 | 14 | 14 |
Package Type | D | N | N | NS |
Industry STD Term | SOIC | PDIP | PDIP | SOP |
JEDEC Code | R-PDSO-G | R-PDIP-T | R-PDIP-T | R-PDSO-G |
Package QTY | 50 | 25 | 2000 | |
Carrier | TUBE | TUBE | LARGE T&R | |
Device Marking | AS280 | SN74AS280N | 74AS280 | |
Width (mm) | 3.91 | 6.35 | 6.35 | 5.3 |
Length (mm) | 8.65 | 19.3 | 19.3 | 10.3 |
Thickness (mm) | 1.58 | 3.9 | 3.9 | 1.95 |
Pitch (mm) | 1.27 | 2.54 | 2.54 | 1.27 |
Max Height (mm) | 1.75 | 5.08 | 5.08 | 2 |
Mechanical Data | Descargar | Descargar | Descargar | Descargar |
Paramétricos
Parameters / Models | SN74AS280D | SN74AS280N | SN74AS280N3 | SN74AS280NSR |
---|---|---|---|---|
Approx. Price (US$) | 1.47 | 1ku | 1.47 | 1ku | ||
Bits | 2 | 2 | ||
Bits(#) | 2 | 2 | ||
F @ Nom Voltage(Max), Mhz | 125 | 125 | ||
F @ Nom Voltage(Max)(Mhz) | 125 | 125 | ||
Function | Parity | Parity | Parity | Parity |
ICC @ Nom Voltage(Max), mA | 35 | 35 | ||
ICC @ Nom Voltage(Max)(mA) | 35 | 35 | ||
Input Type | TTL | |||
Operating Temperature Range, C | 0 to 70 | 0 to 70 | ||
Operating Temperature Range(C) | 0 to 70 | 0 to 70 | ||
Output Drive (IOL/IOH)(Max), mA | 20/-2 | 20/-2 | ||
Output Drive (IOL/IOH)(Max)(mA) | 20/-2 | 20/-2 | ||
Output Type | CMOS | |||
Package Group | SOIC | PDIP | PDIP | SO |
Package Size: mm2:W x L, PKG | See datasheet (PDIP) | 14SO: 80 mm2: 7.8 x 10.2(SO) | ||
Package Size: mm2:W x L (PKG) | See datasheet (PDIP) | See datasheet (PDIP) | ||
Rating | Catalog | Catalog | Catalog | Catalog |
Schmitt Trigger | No | |||
Technology Family | AS | AS | AS | AS |
Type | Other | Other | Other | Other |
VCC(Max), V | 5.5 | 5.5 | ||
VCC(Max)(V) | 5.5 | 5.5 | ||
VCC(Min), V | 4.5 | 4.5 | ||
VCC(Min)(V) | 4.5 | 4.5 | ||
Voltage(Nom), V | 5 | 5 | ||
Voltage(Nom)(V) | 5 | 5 | ||
tpd @ Nom Voltage(Max), ns | 12 | 12 | ||
tpd @ Nom Voltage(Max)(ns) | 12 | 12 |
Plan ecológico
SN74AS280D | SN74AS280N | SN74AS280N3 | SN74AS280NSR | |
---|---|---|---|---|
RoHS | Obediente | Obediente | Desobediente | Obediente |
Pb gratis | Sí | Sí | No |
Notas de aplicación
- Advanced Schottky Load ManagementPDF, 277 Kb, Archivo publicado: feb 1, 1997
Designers of high-speed systems that include advanced Schottky (AS) devices must consider the operating environment in their work. They must be aware of the individual device characteristics and their interaction with other devices. This document provides a detailed discussion of the waveform characteristics equivalent circuit models transmission line fanout and termination for AS load manageme - Advanced Schottky (ALS and AS) Logic FamiliesPDF, 1.9 Mb, Archivo publicado: agosto 1, 1995
This document introduces the advanced Schottky family of clamped TTL integrated circuits (ICs). Detailed electrical characteristics of the 'AS and 'ALS devices with table formats are provided. Guidelines for designing high-performance digital systems using the Advanced Schottky family are given along with a brief summary of the solutions to most design decisions needed to implement systems using t
Linea modelo
Serie: SN74AS280 (4)
Clasificación del fabricante
- Semiconductors> Logic> Specialty Logic> Counter/Arithmetic/Parity Function