Datasheet Texas Instruments SN65LVDS386 — Ficha de datos

Fabricante	Texas Instruments
Serie	SN65LVDS386

Receptor LVDS de 16 canales

Hojas de datos

PDF, 1.7 Mb, Revisión: I, Archivo publicado: jul 29, 2014

Extracto del documento

	SN65LVDS386DGG	SN65LVDS386DGGG4	SN65LVDS386DGGR	SN65LVDS386DGGRG4
Estado del ciclo de vida	Activo (Recomendado para nuevos diseños)	Activo (Recomendado para nuevos diseños)	Activo (Recomendado para nuevos diseños)	Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricante	No	No	No	No

	SN65LVDS386DGG	SN65LVDS386DGGG4	SN65LVDS386DGGR	SN65LVDS386DGGRG4
N	1	2	3	4
Pin	64	64	64	64
Package Type	DGG	DGG	DGG	DGG
Industry STD Term	TSSOP	TSSOP	TSSOP	TSSOP
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	25	25	2000	2000
Carrier	TUBE	TUBE	LARGE T&R	LARGE T&R
Device Marking	LVDS386	LVDS386	LVDS386	LVDS386
Width (mm)	6.1	6.1	6.1	6.1
Length (mm)	17	17	17	17
Thickness (mm)	1.15	1.15	1.15	1.15
Pitch (mm)	.5	.5	.5	.5
Max Height (mm)	1.2	1.2	1.2	1.2
Mechanical Data	Descargar	Descargar	Descargar	Descargar

Parameters / Models	SN65LVDS386DGG	SN65LVDS386DGGG4	SN65LVDS386DGGR	SN65LVDS386DGGRG4
Device Type	Receiver	Receiver	Receiver	Receiver
ESD HBM, kV	15	15	15	15
Function	Receiver	Receiver	Receiver	Receiver
ICC(Max), mA	70	70	70	70
Input Signal	LVDS	LVDS	LVDS	LVDS
No. of Rx	16	16	16	16
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Signal	LVTTL	LVTTL	LVTTL	LVTTL
Package Group	TSSOP	TSSOP	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	64TSSOP: 138 mm2: 8.1 x 17(TSSOP)	64TSSOP: 138 mm2: 8.1 x 17(TSSOP)	64TSSOP: 138 mm2: 8.1 x 17(TSSOP)	64TSSOP: 138 mm2: 8.1 x 17(TSSOP)
Protocols	LVDS	LVDS	LVDS	LVDS
Signaling Rate, Mbps	250	250	250	250

	SN65LVDS386DGG	SN65LVDS386DGGG4	SN65LVDS386DGGR	SN65LVDS386DGGRG4
RoHS	Obediente	Obediente	Obediente	Obediente

Descargar
Using Signaling Rate and Transfer Rate (Rev. A)
PDF, 258 Kb, Revisión: A, Archivo publicado: feb 7, 2005
This document defines data signaling rate and data transfer rate, and it demonstrates the differences between them. Taking the SN65LVDS386 and SN65LVDS387 16-channellow-voltage differential (LVDS) line drivers and receivers with random parallel data of various bandwidths as an example, this document discusses the components that make up the system timing budget and presents empirical data on cro

Serie: SN65LVDS386 (4)