Datasheet Texas Instruments SN65LVDS310 — Ficha de datos

SN65LVDS310
www.ti.com SLLS836 – MAY 2007 PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
FEATURES Serial Interface Technology
Compatible With FlatLinkв„ў 3G Transmitters
(E.g., SN65LVDS305 or SN65LVDS307)
Supports Video Interfaces up to 24-Bit RGB
Data and 3 Control Bits Received Over One
SubLVDS Differential Data Line
SubLVDS Differential Voltage Levels
Up to 405-Mbps Data Throughput
Three Operating Modes to Conserve Power
– Active mode QVGA: 17 mW
– Typical Shutdown: 0.7 µW
– Typical Standby Mode: 67 µW Typical
ESD Rating > 4 kV (HBM)
Pixel-Clock Range of 4 MHz–15 MHz
Failsafe on All CMOS Inputs
Packaged in 4-mm Г— 4-mm MicroStar
Juniorв„ўВµBGAВ® With 0,5-mm Ball Pitch
Very Low EMI When receiving, the PLL locks to the incoming clock,
CLK, and generates an internal high-speed clock at
the line rate of the data lines. The data is serially
loaded into a shift register using the internal …