Datasheet Texas Instruments SN54LVTH373 — Ficha de datos

Fabricante	Texas Instruments
Serie	SN54LVTH373

Hojas de datos

Precios

Estado

Embalaje

Paramétricos

Parameters / Models	5962-9950901Q2A	5962-9950901QRA	5962-9950901QSA	SNJ54LVTH373FK	SNJ54LVTH373J	SNJ54LVTH373W
3-State Output	Yes	Yes	Yes	Yes	Yes	Yes
Bits	8	8	8	8	8	8
F @ Nom Voltage(Max), Mhz	160	160	160	160	160	160
ICC @ Nom Voltage(Max), mA	5	5	5	5	5	5
Input Type	TTL	TTL	TTL	TTL	TTL	TTL
Operating Temperature Range, C	-55 to 125	-55 to 125	-55 to 125	-55 to 125	-55 to 125	-55 to 125
Output Drive (IOL/IOH)(Max), mA	64/-12	64/-12	64/-12	64/-12	64/-12	64/-12
Output Type	TTL	TTL	TTL	TTL	TTL	TTL
Package Group	LCCC	CDIP	CFP	LCCC	CDIP	CFP
Package Size: mm2:W x L, PKG	20LCCC: 79 mm2: 8.89 x 8.89(LCCC)	See datasheet (CDIP)	See datasheet (CFP)	20LCCC: 79 mm2: 8.89 x 8.89(LCCC)	See datasheet (CDIP)	See datasheet (CFP)
Rating	Military	Military	Military	Military	Military	Military
Technology Family	LVT	LVT	LVT	LVT	LVT	LVT
VCC(Max), V	3.6	3.6	3.6	3.6	3.6	3.6
VCC(Min), V	2.7	2.7	2.7	2.7	2.7	2.7
tpd @ Nom Voltage(Max), ns	3.9	3.9	3.9	3.9	3.9	3.9

Plan ecológico

Notas de aplicación

• Descargar
  Input and Output Characteristics of Digital Integrated Circuits
  PDF, 1.7 Mb, Archivo publicado: oct 1, 1996
  This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding the characteristics of the components. This knowledge is particularly useful when for example a decision must be made as to which circuit shou
• Descargar
  LVT Family Characteristics (Rev. A)
  PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
  To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
• Descargar
  LVT-to-LVTH Conversion
  PDF, 84 Kb, Archivo publicado: dic 8, 1998
  Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
• Descargar
  Understanding Advanced Bus-Interface Products Design Guide
  PDF, 253 Kb, Archivo publicado: mayo 1, 1996
• Descargar
  Power-Up Behavior of Clocked Devices (Rev. A)
  PDF, 34 Kb, Revisión: A, Archivo publicado: feb 6, 2015
• Descargar
  TI IBIS File Creation Validation and Distribution Processes
  PDF, 380 Kb, Archivo publicado: agosto 29, 2002
  The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con
• Descargar
  Live Insertion
  PDF, 150 Kb, Archivo publicado: oct 1, 1996
  Many applications require the ability to exchange modules in electronic systems without removing the supply voltage from the module (live insertion). For example an electronic telephone exchange must always remain operational even during module maintenance and repair. To avoid damaging components additional circuitry modifications are necessary. This document describes in detail the phenomena tha
• Descargar
  Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
  PDF, 209 Kb, Archivo publicado: mayo 10, 2002
  Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
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  Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
  PDF, 105 Kb, Revisión: A, Archivo publicado: agosto 1, 1997
  The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
• Descargar
  Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
  PDF, 614 Kb, Revisión: C, Archivo publicado: dic 2, 2015
• Descargar
  Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
  PDF, 337 Kb, Archivo publicado: jul 8, 2004
  Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
• Descargar
  16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
  PDF, 895 Kb, Revisión: B, Archivo publicado: mayo 22, 2002
  TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
• Descargar
  Introduction to Logic
  PDF, 93 Kb, Archivo publicado: abr 30, 2015
• Descargar
  Implications of Slow or Floating CMOS Inputs (Rev. D)
  PDF, 260 Kb, Revisión: D, Archivo publicado: jun 23, 2016

Linea modelo

Clasificación del fabricante

• Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers