Datasheet Texas Instruments SN54F109 — Ficha de datos

FabricanteTexas Instruments
SerieSN54F109
Datasheet Texas Instruments SN54F109

Chanclas JK positivas con borde positivo J / W claras y preestablecidas

Hojas de datos

Dual J-K Positive-Edge-Triggered Flip-Flops w/Clear And Preset datasheet
PDF, 554 Kb, Revisión: A, Archivo publicado: oct 1, 1993
Extracto del documento

Precios

Estado

5962-9758001Q2A5962-9758001QEA5962-9758001QFAJM38510/34102B2AJM38510/34102BEAJM38510/34102BFAM38510/34102B2AM38510/34102BEAM38510/34102BFASNJ54F109FKSNJ54F109JSNJ54F109W
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNoNoNoNoNoNoNoNoNo

Embalaje

5962-9758001Q2A5962-9758001QEA5962-9758001QFAJM38510/34102B2AJM38510/34102BEAJM38510/34102BFAM38510/34102B2AM38510/34102BEAM38510/34102BFASNJ54F109FKSNJ54F109JSNJ54F109W
N123456789101112
Pin201616201616201616201616
Package TypeFKJWFKJWFKJWFKJW
Industry STD TermLCCCCDIPCFPLCCCCDIPCFPLCCCCDIPCFPLCCCCDIPCFP
JEDEC CodeS-CQCC-NR-GDIP-TR-GDFP-FS-CQCC-NR-GDIP-TR-GDFP-FS-CQCC-NR-GDIP-TR-GDFP-FS-CQCC-NR-GDIP-TR-GDFP-F
Package QTY111111111111
CarrierTUBETUBETUBETUBETUBETUBETUBETUBETUBETUBETUBETUBE
Device MarkingSNJ54FSNJ54F109JSNJ54F109W34102B2A34102BEAJM38510/JM38510/34102BEAJM38510/109FKA5962-9758001QF
Width (mm)8.896.926.738.896.926.738.896.926.738.896.926.73
Length (mm)8.8919.5610.38.8919.5610.38.8919.5610.38.8919.5610.3
Thickness (mm)1.834.571.651.834.571.651.834.571.651.834.571.65
Pitch (mm)1.272.541.271.272.541.271.272.541.271.272.541.27
Max Height (mm)2.035.082.032.035.082.032.035.082.032.035.082.03
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargar

Plan ecológico

5962-9758001Q2A5962-9758001QEA5962-9758001QFAJM38510/34102B2AJM38510/34102BEAJM38510/34102BFAM38510/34102B2AM38510/34102BEAM38510/34102BFASNJ54F109FKSNJ54F109JSNJ54F109W
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Notas de aplicación

  • Input and Output Characteristics of Digital Integrated Circuits
    PDF, 1.7 Mb, Archivo publicado: oct 1, 1996
    This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding the characteristics of the components. This knowledge is particularly useful when for example a decision must be made as to which circuit shou
  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revisión: A, Archivo publicado: feb 6, 2015
  • TI IBIS File Creation Validation and Distribution Processes
    PDF, 380 Kb, Archivo publicado: agosto 29, 2002
    The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con
  • Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
    PDF, 105 Kb, Revisión: A, Archivo publicado: agosto 1, 1997
    The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, Revisión: C, Archivo publicado: dic 2, 2015
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, Archivo publicado: jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • Designing With Logic (Rev. C)
    PDF, 186 Kb, Revisión: C, Archivo publicado: jun 1, 1997
    Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w
  • Introduction to Logic
    PDF, 93 Kb, Archivo publicado: abr 30, 2015

Linea modelo

Clasificación del fabricante

  • Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers