Datasheet Texas Instruments DS92LV18TVV/NOPB — Ficha de datos

Serializador / Deserializador LVDS de bus de 18 bits - 15-66 MHz 80-LQFP -40 a 85

Hojas de datos

PDF, 1.3 Mb, Revisión: E, Archivo publicado: abr 18, 2013

Extracto del documento

Estado del ciclo de vida	Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricante	Sí

ESD	2 kV
Function	SerDes
Input Compatibility	LVTTL,BLVDS
Operating Temperature Range	-40 to 85 C
Output Compatibility	LVDS,BLVDS,LVTTL
Package Group	LQFP
Package Size: mm2:W x L	80LQFP: 196 mm2: 14 x 14(LQFP) PKG
Protocols	Channel-Link I
Rating	Catalog
Supply Voltage(s)	3.3 V

RoHS

Obediente

Evaluation Modules & Boards: LVDS-18B-EVK
18-Bit Bus LVDS SERDES Evaluation Board 15-66 MHz
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
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External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A)
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This application report highlights how using external SerDes in conjunction with minimum current driveFPGA I/O can reduce FPGAвЂ™s internal noise and reap the benefits of a serial interface across the system.This may allow designers to use low end FPGAs with external SerDes to reduce cost and still have highanalog performance.
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DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E)
PDF, 170 Kb, Revisión: E, Archivo publicado: abr 29, 2013
Reduction in system size, increase in system performance and savings in system cost are valuablebenefits that SER/DES devices (Serializers and Deserializers) bring to many system designers. Thesebenefits are the reason why SER/DES are integral pieces of many of todayвЂ™s high-speed systems.One of the design constraints for these systems is the maximum transmission distance between a serializer

Serie: DS92LV18 (2)