Datasheet Texas Instruments DS92LV16 — Ficha de datos

FabricanteTexas Instruments
SerieDS92LV16
Datasheet Texas Instruments DS92LV16

Serializador / deserializador de bus LVDS de 16 bits - 25-80 MHz

Hojas de datos

DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz datasheet
PDF, 1.3 Mb, Revisión: H, Archivo publicado: abr 16, 2013
Extracto del documento

Precios

Estado

DS92LV16TVHGDS92LV16TVHG/NOPBDS92LV16TVHGX/NOPB
Estado del ciclo de vidaNRND (No recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNo

Embalaje

DS92LV16TVHGDS92LV16TVHG/NOPBDS92LV16TVHGX/NOPB
N123
Pin808080
Package TypePNPNPN
Industry STD TermLQFPLQFPLQFP
JEDEC CodeS-PQFP-GS-PQFP-GS-PQFP-G
Package QTY1191191000
CarrierTUBETUBELARGE T&R
Device Marking>BDS92LV16TVHGDS92LV16TVHG
Width (mm)121212
Length (mm)121212
Thickness (mm)1.41.41.4
Pitch (mm).5.5.5
Max Height (mm)1.61.61.6
Mechanical DataDescargarDescargarDescargar

Paramétricos

Parameters / ModelsDS92LV16TVHG
DS92LV16TVHG
DS92LV16TVHG/NOPB
DS92LV16TVHG/NOPB
DS92LV16TVHGX/NOPB
DS92LV16TVHGX/NOPB
ESD, kV2.52.52.5
FunctionSerDesSerDesSerDes
Input CompatibilityLVTTL,LVDS,BLVDSLVTTL,LVDS,BLVDSLVTTL,LVDS,BLVDS
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85
Output CompatibilityLVDS,BLVDS,LVTTLLVDS,BLVDS,LVTTLLVDS,BLVDS,LVTTL
Package GroupLQFPLQFPLQFP
Package Size: mm2:W x L, PKG80LQFP: 196 mm2: 14 x 14(LQFP)80LQFP: 196 mm2: 14 x 14(LQFP)80LQFP: 196 mm2: 14 x 14(LQFP)
ProtocolsChannel-Link IChannel-Link IChannel-Link I
RatingCatalogCatalogCatalog
Supply Voltage(s), V3.33.33.3

Plan ecológico

DS92LV16TVHGDS92LV16TVHG/NOPBDS92LV16TVHGX/NOPB
RoHSSee ti.comObedienteObediente

Notas de aplicación

  • How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask (Rev. A)
    PDF, 2.0 Mb, Revisión: A, Archivo publicado: abr 26, 2013
    The following application report contains information that will help you validate signal quality on a BLVDS SER/DES link. How to capture an eye pattern, how to generate an eye mask, and how to validate signal quality are all explained in detail in this document.
  • DS92LV16 Power Up Reset (Rev. B)
    PDF, 26 Kb, Revisión: B, Archivo publicado: abr 26, 2013
    DS92LV16 date code VS39AD and later (middle two date code numbers will be ≥ 39) have a minor metallayer change to the chip’s power up reset and pull up circuitry to ensure robust start up with very slowsupply ramp rates. This change is very minor. It does not affect device functionality, performance, orreliability and requires no re-qualification.All parts sampled or purchased directly fro
  • External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A)
    PDF, 8.3 Mb, Revisión: A, Archivo publicado: abr 26, 2013
    This application report highlights how using external SerDes in conjunction with minimum current driveFPGA I/O can reduce FPGA’s internal noise and reap the benefits of a serial interface across the system.This may allow designers to use low end FPGAs with external SerDes to reduce cost and still have highanalog performance.
  • DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E)
    PDF, 170 Kb, Revisión: E, Archivo publicado: abr 29, 2013
    Reduction in system size, increase in system performance and savings in system cost are valuablebenefits that SER/DES devices (Serializers and Deserializers) bring to many system designers. Thesebenefits are the reason why SER/DES are integral pieces of many of today’s high-speed systems.One of the design constraints for these systems is the maximum transmission distance between a serializer

Linea modelo

Clasificación del fabricante

  • Semiconductors> Interface> Serializer, Deserializer> BLVDS/LVDS SerDes (<100 MHz)