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SNLS011D – JULY 1999 – REVISED AUGUST 2016 DS90LV032A 3-V LVDS Quad CMOS Differential Line Receiver
1 Features 3 Description The DS90LV032A is a quad CMOS differential line
receiver designed for applications requiring ultra-low
power dissipation and high data rates. The device is
designed to support data rates in excess of 400 Mbps
(200 MHz) using Low Voltage Differential Signaling
(LVDS) technology. 1 >400 Mbps (200 MHz) Switching Rates
0.1-ns Channel-to-Channel Skew (Typical)
0.1-ns Differential Skew (Typical)
3.3-ns Maximum Propagation Delay
3.3-V Power Supply Design
Power Down High Impedance on LVDS Inputs
Low Power Design (40 mW at 3.3 V Static)
Interoperable With Existing 5-V LVDS Networks
Accepts Small Swing (350 mV Typical) VID
Supports Open, Short, and Terminated Input FailSafe
Compatible With ANSI/TIA/EIA-644 …
