Datasheet Texas Instruments DS90CR287 — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | DS90CR287 |
Transmisor de enlace de canal de 28 bits LVDS estroboscópico de datos de borde ascendente + 3.3V - 85 MHz
Hojas de datos
DS90CR287/DS90CR288A 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link 85MHz datasheet
PDF, 1.5 Mb, Revisión: G, Archivo publicado: marzo 5, 2013
Extracto del documento
Precios
Estado
| DS90CR287MTD | DS90CR287MTD/NOPB | DS90CR287MTDX/NOPB | DS90CR287SLC/NOPB | |
|---|---|---|---|---|
| Estado del ciclo de vida | NRND (No recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | NRND (No recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No | Sí | No | No |
Embalaje
| DS90CR287MTD | DS90CR287MTD/NOPB | DS90CR287MTDX/NOPB | DS90CR287SLC/NOPB | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 56 | 56 | 56 | 64 |
| Package Type | DGG | DGG | DGG | NZC |
| Industry STD Term | TSSOP | TSSOP | TSSOP | NFBGA |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | S-PBGA-N |
| Package QTY | 34 | 34 | 1000 | 360 |
| Carrier | TUBE | TUBE | LARGE T&R | JEDEC TRAY (10+1) |
| Device Marking | >B | >B | >B | DS90CR287 |
| Width (mm) | 6.1 | 6.1 | 6.1 | 8 |
| Length (mm) | 14 | 14 | 14 | 8 |
| Thickness (mm) | 1.15 | 1.15 | 1.15 | 1.4 |
| Pitch (mm) | .5 | .5 | .5 | .8 |
| Max Height (mm) | 1.2 | 1.2 | 1.2 | 1.5 |
| Mechanical Data | Descargar | Descargar | Descargar | Descargar |
Paramétricos
| Parameters / Models | DS90CR287MTD | DS90CR287MTD/NOPB | DS90CR287MTDX/NOPB | DS90CR287SLC/NOPB |
|---|---|---|---|---|
| Clock Max, MHz | 85 | 85 | 85 | 85 |
| Clock Min, MHz | 20 | 20 | 20 | 20 |
| Compression Ratio | 28 to 4 | 28 to 4 | 28 to 4 | 28 to 4 |
| Data Throughput, Mbps | 2380 | 2380 | 2380 | 2380 |
| ESD, kV | 7 | 7 | 7 | 7 |
| Function | Serializer | Serializer | Serializer | Serializer |
| Input Compatibility | LVCMOS | LVCMOS | LVCMOS | LVCMOS |
| Operating Temperature Range, C | -10 to 70 | -10 to 70 | -10 to 70 | -10 to 70 |
| Output Compatibility | LVDS | LVDS | LVDS | LVDS |
| Package Group | TSSOP | TSSOP | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) |
| Parallel Bus Width, bits | 28 | 28 | 28 | 28 |
| Protocols | Channel-Link I | Channel-Link I | Channel-Link I | Channel-Link I |
| Rating | Catalog | Catalog | Catalog | Catalog |
| Supply Voltage(s), V | 3.3 | 3.3 | 3.3 | 3.3 |
Plan ecológico
| DS90CR287MTD | DS90CR287MTD/NOPB | DS90CR287MTDX/NOPB | DS90CR287SLC/NOPB | |
|---|---|---|---|---|
| RoHS | See ti.com | Obediente | Obediente | Obediente |
Notas de aplicación
- Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A)PDF, 62 Kb, Revisión: A, Archivo publicado: abr 26, 2013
This application note discusses how system designers are able to use Channel Link II ser/Des to improve old and new channel link designs. - CHANNEL LINK Moving and Shaping Information In Point-To-Point ApplicationsPDF, 269 Kb, Archivo publicado: oct 5, 1998
- Multi-Drop Channel-Link OperationPDF, 212 Kb, Archivo publicado: oct 4, 2004
- Receiver Skew Margin for Channel Link I and FPD Link I DevicesPDF, 418 Kb, Archivo publicado: enero 13, 2016
- AN-1108 Channel-Link PCB and Interconnect Design-In GuidelinesPDF, 245 Kb, Archivo publicado: mayo 15, 2004
Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines
Linea modelo
Serie: DS90CR287 (4)
Clasificación del fabricante
- Semiconductors> Interface> Serializer, Deserializer> Channel Link I