Datasheet Texas Instruments DP83640TVV — Ficha de datos

Fabricante	Texas Instruments
Serie	DP83640
Numero de parte	DP83640TVV

Hojas de datos

Precios

Estado

Embalaje

Reemplazos

Paramétricos

Plan ecológico

Kits de diseño y Módulos de evaluación

• Evaluation Modules & Boards: DP83640T-EVK
  DP83640T Evaluation Demo Board
  Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  
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Notas de aplicación

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  Improving Electro-Magnetic Noise Immunity in Serial Communications Systems (Rev. A)
  PDF, 60 Kb, Revisión: A, Archivo publicado: abr 26, 2013
  This application note provides key recommendations for implementing serial communication systems that exceed IEC immunity test standards. To provide an example of highly reliable serial communications system implementation and testing, a Texas Instruments DP83640 Ethernet Physical Layer device was tested for International Electrotechnical Commission (IEC) immunity test compliance. Results from the
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  AN-2006 Synchronizing a DP83640 PTP Master to a GPS Receiver (Rev. A)
  PDF, 35 Kb, Revisión: A, Archivo publicado: abr 26, 2013
  This application report discusses methods of synchronizing the precision time protocol (PTP) clock to aGPS receiver using the DP83640 precision PHYTERв„ў.
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  AN-1794 Using RMII Master Mode (Rev. A)
  PDF, 63 Kb, Revisión: A, Archivo publicado: abr 26, 2013
  Texas Instruments PHYTERВ® family of products incorporate the Reduced Media Independent Interface (RMII) as described in the RMII revision 1.2 specification from the RMII Consortium. This interface may be used to connect a PHY device to a MAC in 10/100 Mb/s systems using a reduced number of pins relative to standard MII. In this mode, data is transferred two bits at a time using a 50 MHz refere
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  DP83640 Synchronous Ethernet Mode: Achieving Sub-ns Accuracy in PTP Applications (Rev. A)
  PDF, 757 Kb, Revisión: A, Archivo publicado: abr 26, 2013
  This application note first provides a summary of empirical results found when master to slave node synchronization is measured with Synchronous Ethernet mode enabled. Background information is then provided describing the operation of and topological constraints associated with Synchronous Ethernet mode. Typical applications are then described, followed by empirical data which clearly demonstrate
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  IEEE 1588 Precision Time Protocol Time Synchronization Performance (Rev. A)
  PDF, 609 Kb, Revisión: A, Archivo publicado: abr 26, 2013
  This application report presents specific time synchronization results from the precision PHYTER.Histograms and oscilloscope plots of these synchronization results are provided, showing the relationshipbetween the slave clock and the master clock.
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  AN-1729 DP83640 IEEE 1588 PTP Synchronized Clock Output (Rev. D)
  PDF, 209 Kb, Revisión: D, Archivo publicado: abr 26, 2013
  The DP83640 provides a highly precise, low-jitter clock output that is frequency-aligned to the masterIEEE 1588 clock and can be phase-aligned as well. Empirical testing shows very low jitter (less than 1 nspeak-to-peak and standard deviation when using the FCO source) and precise phase alignment. Whiletest results show that the FCO has superior long term jitter performance, using the PGM as
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  IEEE 1588 Boundary Clock and Transparent Clock Implementation Using the DP83640 (Rev. A)
  PDF, 98 Kb, Revisión: A, Archivo publicado: abr 26, 2013
  TIs DP83640 precision PHYTERв„ў implements time-critical portions of the IEEE 1588 Precision TimeProtocol (PTP), allowing high precision IEEE 1588 node implementations. These same features can beused to implement multi-port boundary clock (BC) and transparent clock (TC) devices as well.
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  IEEE 1588 Synchronization Over Standard Networks Using the DP83640 (Rev. A)
  PDF, 87 Kb, Revisión: A, Archivo publicado: abr 26, 2013
  This application report describes a method of synchronization that provides much more accuratesynchronization in systems with larger PDV. The method described attempts to detect minimum delays, or'lucky packets'. The method also takes advantage of the DP83640 clock control mechanism to separatelycontrol clock rate and time corrections, minimizing overshoot or wild swings in the accuracy of t
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  AN-1540 Power Measurement of Ethernet Physical Layer Products (Rev. B)
  PDF, 79 Kb, Revisión: B, Archivo publicado: abr 26, 2013
  System designers require accurate component power consumption specifications, for the purposes of thermal management, component selection, and power distribution planning.
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  Reducing Radiated Emissions in Ethernet 10/100 LAN Applications (Rev. A)
  PDF, 70 Kb, Revisión: A, Archivo publicado: abr 26, 2013
  This application report explains how Texas Instruments' PHYTER products help system designers toreduce radiated emissions in Ethernet 10/100 LAN applications.
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  AN-1469 PHYTERВ® Design & Layout Guide (Rev. D)
  PDF, 289 Kb, Revisión: D, Archivo publicado: abr 26, 2013
  This application report describes PHYTERв„ў design and layout guidelines.
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  AN-1548 PHYTER 100 Base-TX Reference Clock Jitter Tolerance (Rev. B)
  PDF, 126 Kb, Revisión: B, Archivo publicado: abr 26, 2013
  The use of a reference clock that is less stable than those directly driven from an oscillator may be required for some applications. In addition, some customer applications may require partnering with devices that operate outside of the IEEE 802.3 standard for transmitted jitter.

Linea modelo

Clasificación del fabricante

• Semiconductors > Interface > Ethernet > Ethernet PHY