Datasheet Texas Instruments DAC5687-EP — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | DAC5687-EP |
Producto mejorado, doble canal, 16 bits, 500-MSPS, 1x-8x convertidor digital a analógico interpolador
Hojas de datos
16-Bit 500 MSPS 2x-8x Interpolating Dual-Channel DAC datasheet
PDF, 2.2 Mb, Archivo publicado: jun 1, 2006
Extracto del documento
Precios
Estado
| DAC5687MPZPEP | V62/06650-01XE | |
|---|---|---|
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No | No |
Embalaje
| DAC5687MPZPEP | V62/06650-01XE | |
|---|---|---|
| N | 1 | 2 |
| Pin | 100 | 100 |
| Package Type | PZP | PZP |
| Industry STD Term | HTQFP | HTQFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G |
| Package QTY | 90 | 90 |
| Carrier | JEDEC TRAY (10+1) | JEDEC TRAY (10+1) |
| Device Marking | DAC5687MPZPEP | DAC5687MPZPEP |
| Width (mm) | 14 | 14 |
| Length (mm) | 14 | 14 |
| Thickness (mm) | 1 | 1 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | Descargar | Descargar |
Paramétricos
| Parameters / Models | DAC5687MPZPEP | V62/06650-01XE |
|---|---|---|
| Architecture | Current Sink | Current Sink |
| DAC Channels | 2 | 2 |
| DNL(Max), +/-LSB | 3 | 3 |
| INL(Max), +/-LSB | 6 | 6 |
| Interface | Parallel CMOS | Parallel CMOS |
| Operating Temperature Range, C | -55 to 125 | -55 to 125 |
| Output Range Max., mA | 20 | 20 |
| Output Range Min., mA | 2 | 2 |
| Output Type | Current | Current |
| Package Group | HTQFP | HTQFP |
| Package Size: mm2:W x L, PKG | 100HTQFP: 256 mm2: 16 x 16(HTQFP) | 100HTQFP: 256 mm2: 16 x 16(HTQFP) |
| Power Consumption(Typ), mW | 1410 | 1410 |
| Rating | HiRel Enhanced Product | HiRel Enhanced Product |
| Reference: Type | Int | Int |
| Resolution, Bits | 16 | 16 |
| SFDR, dB | 80 | 80 |
| SNR, dB | 75 | 75 |
| Sample / Update Rate, MSPS | 500 | 500 |
| Settling Time, µs | 0.012 | 0.012 |
Plan ecológico
| DAC5687MPZPEP | V62/06650-01XE | |
|---|---|---|
| RoHS | Obediente | Obediente |
Notas de aplicación
- High Speed Digital-to-Analog Converters Basics (Rev. A)PDF, 829 Kb, Revisión: A, Archivo publicado: oct 23, 2012
- Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, Archivo publicado: jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
Linea modelo
Serie: DAC5687-EP (2)
Clasificación del fabricante
- Semiconductors> Space & High Reliability> Data Converter> Digital to Analog Converters