Datasheet Texas Instruments CDCV850DGGG4 — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | CDCV850 |
| Numero de parte | CDCV850DGGG4 |
Controlador de reloj diferencial de bucle de bloqueo de fase de 2.5V con interfaz serial de 2 líneas 48-TSSOP -40 a 85
Hojas de datos
2.5-V Phase Lock Loop Clock Driver With 2-Line Serial Interface datasheet
PDF, 798 Kb, Revisión: D, Archivo publicado: abr 10, 2013
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 48 |
| Package Type | DGG |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 40 |
| Carrier | TUBE |
| Device Marking | CDCV850 |
| Width (mm) | 6.1 |
| Length (mm) | 12.5 |
| Thickness (mm) | 1.15 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Descargar |
Paramétricos
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | 30 ps |
| Number of Outputs | 10 |
| Operating Frequency Range(Max) | 140 MHz |
| Operating Frequency Range(Min) | 60 MHz |
| Operating Temperature Range | -40 to 85 C |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) PKG |
| Rating | Catalog |
| VCC | 2.5 V |
| t(phase error) | 180 ps |
| tsk(o) | 75 ps |
Plan ecológico
| RoHS | Obediente |
Notas de aplicación
- HSTL Clock Buffer Using the CDCV850PDF, 35 Kb, Archivo publicado: jul 15, 2002
The demand for driving 1.5-V HSTL signals for high-integrated and low-voltage digital logic is increasing. Most current systems use LVDS, LVPECL, or 2.5-V LVCMOSsignaling levels. Therefore, a solution is needed to convert these clock signals into HSTL signal swing.The purpose this report is to show how to generate an HSTL compliant clock signal using the CDCV850. This clock buffer accepts LV - Using CDC857/CDCV850 toTransform Single-End CLK Signal Into Differential OutputPDF, 437 Kb, Archivo publicado: sept 27, 2000
The CDC857 and the CDCV850 devices are PLL-based differential clock drivers with a maximum operational frequency of 167 MHz. These devices have been designed to support a double-data-rate (DDR) specification and, therefore, they have higher immunity against incoupling common mode noise. However, they require a differential clock input signal.This report shows (a) how to convert a single ended cl
Linea modelo
Serie: CDCV850 (6)
- CDCV850DGG CDCV850DGGG4 CDCV850DGGR CDCV850DGGRG4 CDCV850IDGG CDCV850IDGGG4
Clasificación del fabricante
- Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers