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CDCLVP110VFR

Datasheet Texas Instruments CDCLVP110VFR — Ficha de datos

FabricanteTexas Instruments
SerieCDCLVP110
Numero de parteCDCLVP110VFR
Datasheet Texas Instruments CDCLVP110VFR

1:10 LVPECL / HSTL a LVPECL Controlador de reloj 32-LQFP -40 a 85

Hojas de datos

Descargar
Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver datasheet
PDF, 653 Kb, Revisión: D, Archivo publicado: enero 11, 2011
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin32
Package TypeVF
Industry STD TermLQFP
JEDEC CodeS-PQFP-G
Package QTY1000
CarrierLARGE T&R
Device MarkingCDCLVP110
Width (mm)7
Length (mm)7
Thickness (mm)1.4
Pitch (mm).8
Max Height (mm)1.6
Mechanical DataDescargar

Paramétricos

Additive RMS Jitter(Typ)300 fs
Input Frequency(Max)3500 MHz
Input LevelHSTL,LVPECL
Number of Outputs10
Operating Temperature Range-40 to 85 C
Output Frequency(Max)3500 MHz
Output LevelLVPECL
Package GroupLQFP
Package Size: mm2:W x L32LQFP: 81 mm2: 9 x 9(LQFP) PKG
RatingCatalog
VCC2.5,3.3 V
VCC Out2.5,3.3 V

Plan ecológico

RoHSObediente

Notas de aplicación

  • Descargar
    Advantage of Using TI's Lowest Jitter Differential Clock Buffer
    PDF, 221 Kb, Archivo publicado: agosto 20, 2003
    Advantage of Using TI's Lowest Jitter Differential Clock Buffer at SONET Speed 622.08 MHz
  • Descargar
    PCB Layout Guidelines for CDCLVP110
    PDF, 70 Kb, Archivo publicado: jun 12, 2002
    This application note describes various electrical and thermal performance considerations for TI's CDCLVP110. In addition, it provides recommendations for PCB layout as well as optimizing power consumption in a real system application. Finally, it shows examples of how to estimate the worst case chip temperature.
  • Descargar
    Clocking Design Guidelines: Unused Pins
    PDF, 158 Kb, Archivo publicado: nov 19, 2015
  • Descargar
    DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
    PDF, 135 Kb, Archivo publicado: feb 19, 2003
  • Descargar
    AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
    PDF, 417 Kb, Revisión: C, Archivo publicado: oct 17, 2007
    This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

Linea modelo

Serie: CDCLVP110 (6)

Clasificación del fabricante

  • Semiconductors > Clock and Timing > Clock Buffers > Differential