Datasheet Texas Instruments CDCLVD110 — Ficha de datos
Fabricante | Texas Instruments |
Serie | CDCLVD110 |
Búfer de reloj LVDS de 1 a 10 hasta 900MHz con una desviación mínima para la distribución del reloj
Hojas de datos
Programmable Low-Voltage 1:10 LVDS Clock Driver datasheet
PDF, 513 Kb, Revisión: C, Archivo publicado: enero 14, 2008
Extracto del documento
Precios
Estado
CDCLVD110VF | CDCLVD110VFG4 | CDCLVD110VFR | CDCLVD110VFRG4 | |
---|---|---|---|---|
Estado del ciclo de vida | NRND (No recomendado para nuevos diseños) | NRND (No recomendado para nuevos diseños) | NRND (No recomendado para nuevos diseños) | NRND (No recomendado para nuevos diseños) |
Disponibilidad de muestra del fabricante | No | No | No | No |
Embalaje
CDCLVD110VF | CDCLVD110VFG4 | CDCLVD110VFR | CDCLVD110VFRG4 | |
---|---|---|---|---|
N | 1 | 2 | 3 | 4 |
Pin | 32 | 32 | 32 | 32 |
Package Type | VF | VF | VF | VF |
Industry STD Term | LQFP | LQFP | LQFP | LQFP |
JEDEC Code | S-PQFP-G | S-PQFP-G | S-PQFP-G | S-PQFP-G |
Package QTY | 250 | 250 | 1000 | 1000 |
Carrier | JEDEC TRAY (10+1) | JEDEC TRAY (10+1) | LARGE T&R | LARGE T&R |
Device Marking | CDCLVD110 | CDCLVD110 | CDCLVD110 | CDCLVD110 |
Width (mm) | 7 | 7 | 7 | 7 |
Length (mm) | 7 | 7 | 7 | 7 |
Thickness (mm) | 1.4 | 1.4 | 1.4 | 1.4 |
Pitch (mm) | .8 | .8 | .8 | .8 |
Max Height (mm) | 1.6 | 1.6 | 1.6 | 1.6 |
Mechanical Data | Descargar | Descargar | Descargar | Descargar |
Plan ecológico
CDCLVD110VF | CDCLVD110VFG4 | CDCLVD110VFR | CDCLVD110VFRG4 | |
---|---|---|---|---|
RoHS | Obediente | Obediente | Obediente | Obediente |
Notas de aplicación
- Benefits of Using TI's Non-PLL Clock Buffer: Best in Class Phase Noise/PhasePDF, 560 Kb, Archivo publicado: jul 18, 2003
This application report presents various jitter and phase noise measurements of three differential clock drivers. A Texas Instruments device was compared to two independent competitor devices. This report proves that clock buffer selection does have an impact on the total system timing budget, particularly when the system has two different input signals connected. Buffers must be able to resist th - DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CMLPDF, 135 Kb, Archivo publicado: feb 19, 2003
- AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)PDF, 417 Kb, Revisión: C, Archivo publicado: oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16
Linea modelo
Serie: CDCLVD110 (4)
Clasificación del fabricante
- Semiconductors> Clock and Timing> Clock Buffers> Differential