Datasheet Texas Instruments CDC706 — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | CDC706 |
Sintetizador / multiplicador / divisor de reloj 3-PLL programado personalizado
Hojas de datos
Programmable 3-PLL Clock Synthesizer / Multiplier / Divider datasheet
PDF, 1.4 Mb, Revisión: B, Archivo publicado: feb 11, 2008
Extracto del documento
Precios
Estado
| CDC706PW | CDC706PWG4 | CDC706PWR | CDC706PWRG4 | |
|---|---|---|---|---|
| Estado del ciclo de vida | NRND (No recomendado para nuevos diseños) | NRND (No recomendado para nuevos diseños) | NRND (No recomendado para nuevos diseños) | NRND (No recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No | No | No | No |
Embalaje
| CDC706PW | CDC706PWG4 | CDC706PWR | CDC706PWRG4 | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 20 | 20 | 20 | 20 |
| Package Type | PW | PW | PW | PW |
| Industry STD Term | TSSOP | TSSOP | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 70 | 70 | 2000 | 2000 |
| Carrier | TUBE | TUBE | LARGE T&R | LARGE T&R |
| Device Marking | CDC706 | CDC706 | CDC706 | CDC706 |
| Width (mm) | 4.4 | 4.4 | 4.4 | 4.4 |
| Length (mm) | 6.5 | 6.5 | 6.5 | 6.5 |
| Thickness (mm) | 1 | 1 | 1 | 1 |
| Pitch (mm) | .65 | .65 | .65 | .65 |
| Max Height (mm) | 1.2 | 1.2 | 1.2 | 1.2 |
| Mechanical Data | Descargar | Descargar | Descargar | Descargar |
Plan ecológico
| CDC706PW | CDC706PWG4 | CDC706PWR | CDC706PWRG4 | |
|---|---|---|---|---|
| RoHS | Obediente | Obediente | Obediente | Obediente |
Notas de aplicación
- CDCx706/x906 Termination and Signal Integrity Guidelines (Rev. A)PDF, 155 Kb, Revisión: A, Archivo publicado: nov 28, 2007
This application report shows and evaluates different schemes for the CDCE706, CDCE906, CDC706, and CDC906. Guidelines for optimizing the series termination are discussed. Additionally, this report describes how the CDCx706/x906 family can be used to drive 1.8-V clock inputs. - High Speed Layout Guidelines (Rev. A)PDF, 762 Kb, Revisión: A, Archivo publicado: agosto 8, 2017
Thisapplicationreportaddresseshigh-speedsignals,suchas clocksignalsand theirrouting,and givesdesignersa reviewof the importantcoherences.Withsomesimplerules,electromagneticinterferenceproblemscan be minimizedwithoutusingcomplicatedformulasand expensivesimulationtools.Section1givesa shortintroductionto theory,whileSection - Clock Recommendations for the DM643x EVMPDF, 121 Kb, Archivo publicado: nov 29, 2006
The DM643x evaluation module (EVM) requires several clock frequencies to run the system properly. The current clocking proposal of the low-cost EVM consists of the VCXO chip PI6CX100-27W, the PLL chip PLL1705, several bus drivers, and a few oscillaors and crystals. This application report discusses several optimized clocking proposals with the Texas Instruments new clock drivers and recommends a m
Linea modelo
Serie: CDC706 (4)
Clasificación del fabricante
- Semiconductors> Clock and Timing> Clock Generators> General Purpose