Datasheet Texas Instruments CDC2510PWR — Ficha de datos

FabricanteTexas Instruments
SerieCDC2510
Numero de parteCDC2510PWR
Datasheet Texas Instruments CDC2510PWR

3.3-V Controlador de reloj de bucle de bloqueo de fase 24-TSSOP

Hojas de datos

CDC2510: 3.3-V Phase-Lock Loop Clock Driver datasheet
PDF, 608 Kb, Revisión: B, Archivo publicado: dic 2, 2004
Extracto del documento

Precios

Estado

Estado del ciclo de vidaNRND (No recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin24
Package TypePW
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingCK2510
Width (mm)4.4
Length (mm)7.8
Thickness (mm)1
Pitch (mm).65
Max Height (mm)1.2
Mechanical DataDescargar

Plan ecológico

RoHSObediente

Notas de aplicación

  • Understanding the Differences Between CDC2509x/10x Devices
    PDF, 65 Kb, Archivo publicado: enero 8, 1999
    This application note provides information concerning the various revisions of the TI CDC2509/10 family of devices. In addition, it will assist designers with new and existing designs. Phase error information, both slope and absolute value, is provided to assist in the tuning process. Furthermore, a table summarizes important parameters for choosing the correct PLL. The table contains capacitance
  • High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)
    PDF, 109 Kb, Revisión: A, Archivo publicado: sept 23, 1998
    The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo

Linea modelo

Serie: CDC2510 (2)

Clasificación del fabricante

  • Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers