Datasheet Texas Instruments CDC2509APWRG4 — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | CDC2509A |
| Numero de parte | CDC2509APWRG4 |
Controlador de reloj de bucle de bloqueo de fase de 3,3 V con salidas de 3 estados 24-TSSOP 0 a 70
Hojas de datos
CDC2509A: 3.3 V Phase Lock Loop Clock Driver (Rev. C)
PDF, 614 Kb, Revisión: C, Archivo publicado: dic 2, 2004
Precios
Estado
| Estado del ciclo de vida | NRND (No recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 24 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | CK2509A |
| Width (mm) | 4.4 |
| Length (mm) | 7.8 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Descargar |
Plan ecológico
| RoHS | Obediente |
| Pb gratis | Sí |
Notas de aplicación
- Using CDC2509A/CDC2510A PLL With Spread Spectrum Clocking (SSC)PDF, 454 Kb, Archivo publicado: enero 5, 1999
This application note describes the CDC2509A/2510A [1] phase-lock loop clockdrivers and their use with spread spectrum clocking system. This application note gives SSC system performance measurements and parameter measurementinstructions. - High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)PDF, 109 Kb, Revisión: A, Archivo publicado: sept 23, 1998
The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo
Linea modelo
Serie: CDC2509A (2)
- CDC2509APWR CDC2509APWRG4
Clasificación del fabricante
- Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers