Datasheet Texas Instruments CDC208DWRG4 — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | CDC208 |
| Numero de parte | CDC208DWRG4 |
Controlador de reloj de 5V doble 1 a 4 20-SOIC
Hojas de datos
Dual 1-Line To 4-Line Clock Drivers With 3-State Outputs datasheet
PDF, 1.1 Mb, Revisión: F, Archivo publicado: oct 28, 1998
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 20 |
| Package Type | DW |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | CDC208 |
| Width (mm) | 7.5 |
| Length (mm) | 12.8 |
| Thickness (mm) | 2.35 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 2.65 |
| Mechanical Data | Descargar |
Paramétricos
| Input Frequency(Max) | 60 MHz |
| Input Level | TTL |
| Number of Outputs | 8 |
| Operating Temperature Range | -40 to 85 C |
| Output Frequency(Max) | 60 MHz |
| Output Level | CMOS |
| Package Group | SOIC |
| Package Size: mm2:W x L | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) PKG |
| Rating | Catalog |
| VCC Out | 5 V |
Plan ecológico
| RoHS | Obediente |
Notas de aplicación
- Minimizing Clock Driver Output Skew Using Ganged OutputsPDF, 53 Kb, Archivo publicado: enero 1, 1994
This document helps designers use existing clock-driver products to drive large loads while maintaining a minimum amount of skew between the device outputs. The emphasis of this document is using parallel or ganged outputs to drive loads. A performance evaluation of the CDC201 is provided.
Linea modelo
Serie: CDC208 (8)
- CDC208DW CDC208DWG4 CDC208DWR CDC208DWRG4 CDC208NS CDC208NSG4 CDC208NSR CDC208NSRG4
Clasificación del fabricante
- Semiconductors > Clock and Timing > Clock Buffers > Single-Ended