Datasheet Texas Instruments CD74AC00 — Ficha de datos
Fabricante | Texas Instruments |
Serie | CD74AC00 |
Puertas NAND Quad de 2 entradas
Hojas de datos
Quadruple 2-Input Positive-NAND Gates datasheet
PDF, 981 Kb, Revisión: C, Archivo publicado: jun 12, 2002
Extracto del documento
Precios
Estado
CD74AC00E | CD74AC00EE4 | CD74AC00M | CD74AC00M96 | CD74AC00MG4 | |
---|---|---|---|---|---|
Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) |
Disponibilidad de muestra del fabricante | No | No | No | No | No |
Embalaje
CD74AC00E | CD74AC00EE4 | CD74AC00M | CD74AC00M96 | CD74AC00MG4 | |
---|---|---|---|---|---|
N | 1 | 2 | 3 | 4 | 5 |
Pin | 14 | 14 | 14 | 14 | 14 |
Package Type | N | N | D | D | D |
Industry STD Term | PDIP | PDIP | SOIC | SOIC | SOIC |
JEDEC Code | R-PDIP-T | R-PDIP-T | R-PDSO-G | R-PDSO-G | R-PDSO-G |
Package QTY | 25 | 25 | 50 | 2500 | 50 |
Carrier | TUBE | TUBE | TUBE | LARGE T&R | TUBE |
Device Marking | CD74AC00E | CD74AC00E | AC00M | AC00M | AC00M |
Width (mm) | 6.35 | 6.35 | 3.91 | 3.91 | 3.91 |
Length (mm) | 19.3 | 19.3 | 8.65 | 8.65 | 8.65 |
Thickness (mm) | 3.9 | 3.9 | 1.58 | 1.58 | 1.58 |
Pitch (mm) | 2.54 | 2.54 | 1.27 | 1.27 | 1.27 |
Max Height (mm) | 5.08 | 5.08 | 1.75 | 1.75 | 1.75 |
Mechanical Data | Descargar | Descargar | Descargar | Descargar | Descargar |
Paramétricos
Parameters / Models | CD74AC00E | CD74AC00EE4 | CD74AC00M | CD74AC00M96 | CD74AC00MG4 |
---|---|---|---|---|---|
Bits | 4 | 4 | 4 | 4 | 4 |
F @ Nom Voltage(Max), Mhz | 100 | 100 | 100 | 100 | 100 |
ICC @ Nom Voltage(Max), mA | 0.08 | 0.08 | 0.08 | 0.08 | 0.08 |
Operating Temperature Range, C | -55 to 125 | -55 to 125 | -55 to 125 | -55 to 125 | -55 to 125 |
Output Drive (IOL/IOH)(Max), mA | 24/-24 | 24/-24 | 24/-24 | 24/-24 | 24/-24 |
Package Group | PDIP | PDIP | SOIC | SOIC | SOIC |
Package Size: mm2:W x L, PKG | See datasheet (PDIP) | See datasheet (PDIP) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) |
Rating | Catalog | Catalog | Catalog | Catalog | Catalog |
Schmitt Trigger | No | No | No | No | No |
Technology Family | AC | AC | AC | AC | AC |
VCC(Max), V | 5.5 | 5.5 | 5.5 | 5.5 | 5.5 |
VCC(Min), V | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 |
Voltage(Nom), V | 1.5,3.3,5 | 1.5,3.3,5 | 1.5,3.3,5 | 1.5,3.3,5 | 1.5,3.3,5 |
tpd @ Nom Voltage(Max), ns | 83,9.3,6.6 | 83,9.3,6.6 | 83,9.3,6.6 | 83,9.3,6.6 | 83,9.3,6.6 |
Plan ecológico
CD74AC00E | CD74AC00EE4 | CD74AC00M | CD74AC00M96 | CD74AC00MG4 | |
---|---|---|---|---|---|
RoHS | Obediente | Obediente | Obediente | Obediente | Obediente |
Pb gratis | Sí | Sí |
Notas de aplicación
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, Archivo publicado: abr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
Linea modelo
Serie: CD74AC00 (5)
Clasificación del fabricante
- Semiconductors> Logic> Gate> NAND Gate