Datasheet Texas Instruments CD54ACT573 — Ficha de datos

Fabricante	Texas Instruments
Serie	CD54ACT573

Cierre transparente octal no inversor con salidas de 3 estados

Hojas de datos

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PDF, 1.3 Mb, Archivo publicado: dic 3, 1998

Extracto del documento

Data sheet acquired from Harris Semiconductor
SCHS291 This data sheet is applicable to the CD74AC563, CD54/74AC573, and CD54/74ACT573. The CD54AC563 and CD54/74ACT563 were
not acquired from Harris Semiconductor. PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION
Orderable Device Status
(1) Package Type Package Pins Package
Drawing
Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (В°C) Device Marking
(4/5) CD54AC573F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 CD54AC573F3A CD54ACT573F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 CD54ACT573F3A CD74AC573E ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74AC573E CD74AC573M ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC573M CD74AC573M96 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC573M CD74AC573M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC573M CD74AC573M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC573M CD74AC573MG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC573M CD74ACT573E ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74ACT573E CD74ACT573EE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74ACT573E CD74ACT573M ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT573M CD74ACT573M96 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT573M CD74ACT573MG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT573M (1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available. …

Precios

Estado

	CD54ACT573F3A
Estado del ciclo de vida	Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricante	No

Embalaje

	CD54ACT573F3A
N	1
Pin	20
Package Type	J
Industry STD Term	CDIP
JEDEC Code	R-GDIP-T
Package QTY	1
Carrier	TUBE
Device Marking	CD54ACT573F3A
Width (mm)	6.92
Length (mm)	24.2
Thickness (mm)	4.57
Pitch (mm)	2.54
Max Height (mm)	5.08
Mechanical Data	Descargar

Paramétricos

Parameters / Models	CD54ACT573F3A
3-State Output	Yes
Bits	8
F @ Nom Voltage(Max), Mhz	90
ICC @ Nom Voltage(Max), mA	0.04
Input Type	TTL
Operating Temperature Range, C	-55 to 125
Output Drive (IOL/IOH)(Max), mA	24/-24
Output Type	CMOS
Package Group	CDIP
Package Size: mm2:W x L, PKG	See datasheet (CDIP)
Rating	Military
Technology Family	ACT
VCC(Max), V	5.5
VCC(Min), V	4.5
tpd @ Nom Voltage(Max), ns	12

Plan ecológico

	CD54ACT573F3A
RoHS	See ti.com

Notas de aplicación

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Selecting the Right Level Translation Solution (Rev. A)
PDF, 313 Kb, Revisión: A, Archivo publicado: jun 22, 2004
Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
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Power-Up Behavior of Clocked Devices (Rev. A)
PDF, 34 Kb, Revisión: A, Archivo publicado: feb 6, 2015
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Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
PDF, 43 Kb, Archivo publicado: abr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Linea modelo

Serie: CD54ACT573 (1)

CD54ACT573F3A

Clasificación del fabricante

Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers