Datasheet Texas Instruments ADS8413 — Ficha de datos

Fabricante	Texas Instruments
Serie	ADS8413

Hojas de datos

Precios

Estado

Embalaje

Paramétricos

Parameters / Models	ADS8413IBRGZR	ADS8413IBRGZRG4	ADS8413IBRGZT	ADS8413IRGZR	ADS8413IRGZRG4	ADS8413IRGZT	ADS8413IRGZTG4
# Input Channels	1	1	1	1	1	1	1
Analog Voltage AVDD(Max), V			5.25
Analog Voltage AVDD(Max)(V)	5.25	5.25		5.25	5.25	5.25	5.25
Analog Voltage AVDD(Min), V			4.75
Analog Voltage AVDD(Min)(V)	4.75	4.75		4.75	4.75	4.75	4.75
Approx. Price (US$)	21.35 | 1ku	21.35 | 1ku		21.35 | 1ku	21.35 | 1ku	21.35 | 1ku	21.35 | 1ku
Architecture	SAR	SAR	SAR	SAR	SAR	SAR	SAR
Digital Supply(Max), V			5.25
Digital Supply(Max)(V)	5.25	5.25		5.25	5.25	5.25	5.25
Digital Supply(Min), V			2.7
Digital Supply(Min)(V)	2.7	2.7		2.7	2.7	2.7	2.7
INL(Max), +/-LSB			2
INL(Max)(+/-LSB)	2	2		2	2	2	2
Input Range(Max), V			4.2
Input Range(Max)(V)	4.096	4.096		4.096	4.096	4.096	4.096
Input Range(Min), V			4.2
Input Type	Differential	Differential	Differential	Differential	Differential	Differential	Differential
Integrated Features	Daisy-Chainable Oscillator	Daisy-Chainable Oscillator	Daisy-Chainable,Oscillator	Daisy-Chainable Oscillator	Daisy-Chainable Oscillator	Daisy-Chainable Oscillator	Daisy-Chainable Oscillator
Interface	Parallel	Parallel	Parallel	Parallel	Parallel	Parallel	Parallel
Multi-Channel Configuration	N/A	N/A	N/A	N/A	N/A	N/A	N/A
Operating Temperature Range, C			-40 to 85
Operating Temperature Range(C)	-40 to 85	-40 to 85		-40 to 85	-40 to 85	-40 to 85	-40 to 85
Package Group	VQFN	VQFN	VQFN	VQFN	VQFN	VQFN	VQFN
Package Size: mm2:W x L, PKG			48VQFN: 49 mm2: 7 x 7(VQFN)
Package Size: mm2:W x L (PKG)	48VQFN: 49 mm2: 7 x 7(VQFN)	48VQFN: 49 mm2: 7 x 7(VQFN)		48VQFN: 49 mm2: 7 x 7(VQFN)	48VQFN: 49 mm2: 7 x 7(VQFN)	48VQFN: 49 mm2: 7 x 7(VQFN)	48VQFN: 49 mm2: 7 x 7(VQFN)
Power Consumption(Typ), mW			290
Power Consumption(Typ)(mW)	155	155		155	155	155	155
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Reference Mode	Ext Int	Ext Int	Ext,Int	Ext Int	Ext Int	Ext Int	Ext Int
Resolution, Bits			16
Resolution(Bits)	16	16		16	16	16	16
SINAD, dB			92
SINAD(dB)	92	92		92	92	92	92
SNR, dB			92
SNR(dB)	92	92		92	92	92	92
Sample Rate (max), SPS			2MSPS
Sample Rate (max)(SPS)	2MSPS	2MSPS		2MSPS	2MSPS	2MSPS	2MSPS
Sample Rate(Max), MSPS			2
THD(Typ), dB			-107
THD(Typ)(dB)	-107	-107		-107	-107	-107	-107

Plan ecológico

Notas de aplicación

• Descargar
  Connecting ADS8410/13 With Long Cable
  PDF, 773 Kb, Archivo publicado: dic 2, 2005
  Many applications require that the analog-to-digital converter (ADC) be located near the field sensor; however, the digital processing often occurs at a distance. Therefore, the input and output signals need to travel through a long cable from the field sensor to the site where digital processing occurs. This application report is a guide for using a 1-meter cable, the Samtec EQCD Series high data
• Descargar
  Using ADS8410/13 in Daisy Chain Mode
  PDF, 3.2 Mb, Archivo publicado: mayo 22, 2006
  Many applications require multiple analog-to-digital converters (ADC) in a system. Daisy chaining multiple ADCs enables the use of a single data receiver or a small FPGA. It offers easy and minimal digital routing. This application report describes how multiple ADCs (ADS8410/13) work in a daisy-chain mode. The device offers a high-speed (200 Mbps) LVDS serial interface. This application report als
• Descargar
  Using ADS8410/13 in Cascade Mode
  PDF, 2.9 Mb, Archivo publicado: jun 8, 2006
  Many applications require multiple analog-to-digital converters (ADC) in a system. Cascading multiple ADCs enables the use of a single data receiver or a small FPGA. This offers lower power consumption and independent ADC usage. This application report describes how multiple ADCs (ADS8410/13) work in a cascade mode. The ADS8410/13 integrated circuit offers a high-speed (200 Mbps) LVDS serial inter
• Descargar
  Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
  PDF, 227 Kb, Revisión: A, Archivo publicado: nov 10, 2010
  This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
• Descargar
  Determining Minimum Acquisition Times for SAR ADCs, part 2
  PDF, 215 Kb, Archivo publicado: marzo 17, 2011
  The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

Linea modelo

Clasificación del fabricante

• Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)