Datasheet Texas Instruments ADS820 — Ficha de datos

Fabricante	Texas Instruments
Serie	ADS820

Hojas de datos

Precios

Estado

Embalaje

Paramétricos

Parameters / Models	ADS820E	ADS820E/1K	ADS820U	ADS820UG4
# Input Channels	1	1	1	1
Analog Input BW, MHz			65
Analog Input BW(MHz)	65	65		65
Approx. Price (US$)	10.15 | 1ku	10.15 | 1ku		10.15 | 1ku
Architecture	Pipeline	Pipeline	Pipeline	Pipeline
DNL(Max), +/-LSB			1
DNL(Max)(+/-LSB)	1	1		1
DNL(Typ), +/-LSB			0.15
ENOB, Bits			9.5
ENOB(Bits)	9.5	9.5		9.5
INL(Max), +/-LSB			2
INL(Max)(+/-LSB)	2	2		2
INL(Typ), +/-LSB			0.5
Input Buffer	No	No	No
Input Range	2V (p-p)	2V (p-p)	2	2V (p-p)
Interface	Parallel CMOS	Parallel CMOS	Parallel CMOS	Parallel CMOS
Operating Temperature Range, C			-40 to 85
Operating Temperature Range(C)	-40 to 85	-40 to 85		-40 to 85
Package Group	SOIC	SOIC	SOIC	SOIC
Package Size(mm2=WxL)				28SOIC: 184 mm2: 10.3 x 17.9
Package Size: mm2:W x L, PKG			28SOIC: 184 mm2: 10.3 x 17.9(SOIC)
Package Size: mm2:W x L (PKG)	28SOIC: 184 mm2: 10.3 x 17.9(SOIC)	28SOIC: 184 mm2: 10.3 x 17.9(SOIC)
Power Consumption(Typ), mW			200
Power Consumption(Typ)(mW)	200	200		200
Rating	Catalog	Catalog	Catalog	Catalog
Reference Mode	Ext Int	Ext Int	Ext,Int	Int Ext
Resolution, Bits			10
Resolution(Bits)	10	10		10
SFDR, dB			62
SFDR(dB)	62	62		62
SINAD, dB			60
SINAD(dB)	60	60		60
SNR, dB			60
SNR(dB)	60	60		60
Sample Rate (max)(SPS)				20MSPS
Sample Rate(Max), MSPS			20
Sample Rate(Max)(MSPS)	20	20

Plan ecológico

Notas de aplicación

• Descargar
  ADS82x ADC with non-uniform sampling clock
  PDF, 234 Kb, Archivo publicado: feb 28, 2005
• Descargar
  CDCE62005 as Clock Solution for High-Speed ADCs
  PDF, 805 Kb, Archivo publicado: sept 4, 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
• Descargar
  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, Archivo publicado: abr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
• Descargar
  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
• Descargar
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
• Descargar
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, Archivo publicado: jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
• Descargar
  Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
  PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015
• Descargar
  A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
  PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
  This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
• Descargar
  Principles of Data Acquisition and Conversion (Rev. A)
  PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015
• Descargar
  Interleaving Analog-to-Digital Converters
  PDF, 64 Kb, Archivo publicado: oct 2, 2000
  It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration several possible sources of error.
• Descargar
  What Designers Should Know About Data Converter Drift
  PDF, 95 Kb, Archivo publicado: oct 2, 2000
  Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its operating-temperature extremes, perhaps only to 9 or even 8 bits. But for lack of more precise knowledge, many play it safe (and expensive) and overspecify.

Linea modelo

Clasificación del fabricante

• Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)