Datasheet Texas Instruments ADS807 — Ficha de datos

Fabricante	Texas Instruments
Serie	ADS807

Hojas de datos

Precios

Estado

Embalaje

Paramétricos

Parameters / Models	ADS807E	ADS807E/1K	ADS807EG4
# Input Channels	1	1	1
Analog Input BW, MHz	270	270
Analog Input BW(MHz)			270
Approx. Price (US$)			13.66 | 1ku
Architecture	Pipeline	Pipeline	Pipeline
DNL(Max), +/-LSB	1	1
DNL(Max)(+/-LSB)			1
DNL(Typ), +/-LSB	0.5	0.5
ENOB, Bits	10.2	10.2
ENOB(Bits)			0.5
INL(Max), +/-LSB	4	4
INL(Max)(+/-LSB)			2
INL(Typ), +/-LSB	2	2
Input Buffer	No	No
Input Range	2,3	2,3	2V / 3V (p-p)
Interface	Parallel CMOS	Parallel CMOS	Parallel CMOS
Operating Temperature Range, C	-40 to 85	-40 to 85
Operating Temperature Range(C)			-40 to 85
Package Group	SSOP	SSOP	SSOP
Package Size(mm2=WxL)			28SSOP: 80 mm2: 7.8 x 10.2
Package Size: mm2:W x L, PKG	28SSOP: 80 mm2: 7.8 x 10.2(SSOP)	28SSOP: 80 mm2: 7.8 x 10.2(SSOP)
Power Consumption(Typ), mW	335	335
Power Consumption(Typ)(mW)			335
Rating	Catalog	Catalog	Catalog
Reference Mode	Ext,Int	Ext,Int	Int Ext
Resolution, Bits	12	12
Resolution(Bits)			12
SFDR, dB	82	82
SFDR(dB)			82
SINAD, dB	69	69
SINAD(dB)			69
SNR, dB	69	69
SNR(dB)			69
Sample Rate (max)(SPS)			53MSPS
Sample Rate(Max), MSPS	53	53

Plan ecológico

Notas de aplicación

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  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
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  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
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  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
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  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
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  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, Archivo publicado: jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
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  PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015
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  A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
  PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
  This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
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  Principles of Data Acquisition and Conversion (Rev. A)
  PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015
• Descargar
  CDCE62005 as Clock Solution for High-Speed ADCs
  PDF, 805 Kb, Archivo publicado: sept 4, 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527, which is capable of sampling up to 210 MSPS. To realize the full potential of thes
• Descargar
  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, Archivo publicado: abr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs
• Descargar
  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies
• Descargar
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the refe
• Descargar
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, Archivo publicado: jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed, high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483, which is capable of
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  Principles of Data Acquisition and Conversion (Rev. A)
  PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015
  AB-082 Principles of Data Acquisition and Conversion
• Descargar
  Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
  PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015
  AB-084 Analog-to-Digital Grounding Practices Affect System Performance
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  Interleaving Analog-to-Digital Converters
  PDF, 64 Kb, Archivo publicado: oct 2, 2000
  It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration s
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  A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
  PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
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  Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its oper

Linea modelo

Clasificación del fabricante

• Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)