Datasheet Texas Instruments ADS5560 — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | ADS5560 |
Convertidor analógico a digital (ADC) de 16 bits y 40 MSPS
Hojas de datos
ADS556x 16-Bit, 40 and 80 MSPS ADCs With DDR LVDS and CMOS Outputs datasheet
PDF, 1.7 Mb, Revisión: B, Archivo publicado: enero 13, 2016
Extracto del documento
Precios
Estado
| ADS5560IRGZR | ADS5560IRGZT | |
|---|---|---|
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | Sí | No |
Embalaje
| ADS5560IRGZR | ADS5560IRGZT | |
|---|---|---|
| N | 1 | 2 |
| Pin | 48 | 48 |
| Package Type | RGZ | RGZ |
| Industry STD Term | VQFN | VQFN |
| JEDEC Code | S-PQFP-N | S-PQFP-N |
| Package QTY | 2500 | 250 |
| Carrier | LARGE T&R | SMALL T&R |
| Device Marking | AZ5560 | AZ5560 |
| Width (mm) | 7 | 7 |
| Length (mm) | 7 | 7 |
| Thickness (mm) | .9 | .9 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1 | 1 |
| Mechanical Data | Descargar | Descargar |
Paramétricos
| Parameters / Models | ADS5560IRGZR | ADS5560IRGZT |
|---|---|---|
| # Input Channels | 1 | 1 |
| Analog Input BW, MHz | 250 | 250 |
| Architecture | Pipeline | Pipeline |
| DNL(Max), +/-LSB | 3 | 3 |
| DNL(Typ), +/-LSB | 0.5 | 0.5 |
| ENOB, Bits | 13.5 | 13.5 |
| INL(Max), +/-LSB | 8.5 | 8.5 |
| INL(Typ), +/-LSB | 3 | 3 |
| Input Buffer | No | No |
| Input Range, Vp-p | 3.6 | 3.6 |
| Interface | Parallel CMOS,Parallel LVDS | Parallel CMOS,Parallel LVDS |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 |
| Package Group | VQFN | VQFN |
| Package Size: mm2:W x L, PKG | 48VQFN: 49 mm2: 7 x 7(VQFN) | 48VQFN: 49 mm2: 7 x 7(VQFN) |
| Power Consumption(Typ), mW | 674 | 674 |
| Rating | Catalog | Catalog |
| Reference Mode | Ext,Int | Ext,Int |
| Resolution, Bits | 16 | 16 |
| SFDR, dB | 90 | 90 |
| SINAD, dB | 83.2 | 83.2 |
| SNR, dB | 84.3 | 84.3 |
| Sample Rate(Max), MSPS | 40 | 40 |
Plan ecológico
| ADS5560IRGZR | ADS5560IRGZT | |
|---|---|---|
| RoHS | Obediente | Obediente |
Notas de aplicación
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- Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Mb, Revisión: A, Archivo publicado: jul 19, 2013
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This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, Archivo publicado: jun 8, 2008
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- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015
Linea modelo
Serie: ADS5560 (2)
Clasificación del fabricante
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)