Datasheet Texas Instruments ADS5263 — Ficha de datos

FabricanteTexas Instruments
SerieADS5263
Datasheet Texas Instruments ADS5263

Convertidor analógico a digital de cuatro canales, 16 bits, 100 MSPS (ADC)

Hojas de datos

ADS5263 Quad Channel 16-Bit, 100-MSPS High-SNR ADC datasheet
PDF, 2.7 Mb, Revisión: D, Archivo publicado: nov 30, 2015
Extracto del documento

Precios

Estado

ADS5263IRGCRADS5263IRGCR-NMADS5263IRGCTADS5263IRGCT-NM
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNo

Embalaje

ADS5263IRGCRADS5263IRGCR-NMADS5263IRGCTADS5263IRGCT-NM
N1234
Pin64646464
Package TypeRGCRGCRGCRGC
Industry STD TermVQFNVQFNVQFNVQFN
JEDEC CodeS-PQFP-NS-PQFP-NS-PQFP-NS-PQFP-N
Package QTY20002000250250
CarrierLARGE T&RLARGE T&RSMALL T&RSMALL T&R
Device MarkingADS5263ADS5263NMADS5263ADS5263NM
Width (mm)9999
Length (mm)9999
Thickness (mm).88.88.88.88
Pitch (mm).5.5.5.5
Max Height (mm)1111
Mechanical DataDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsADS5263IRGCR
ADS5263IRGCR
ADS5263IRGCR-NM
ADS5263IRGCR-NM
ADS5263IRGCT
ADS5263IRGCT
ADS5263IRGCT-NM
ADS5263IRGCT-NM
# Input Channels4444
Analog Input BW, MHz70707070
ArchitecturePipelinePipelinePipelinePipeline
DNL(Max), +/-LSB0.10.10.10.1
DNL(Typ), +/-LSB0.10.10.10.1
ENOB, Bits12.712.712.712.7
INL(Max), +/-LSB12121212
INL(Typ), +/-LSB5555
Input BufferNoNoNoNo
Input Range, Vp-p4444
InterfaceParallel LVDSParallel LVDSParallel LVDSParallel LVDS
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85
Package GroupVQFNVQFNVQFNVQFN
Package Size: mm2:W x L, PKG64VQFN: 81 mm2: 9 x 9(VQFN)64VQFN: 81 mm2: 9 x 9(VQFN)64VQFN: 81 mm2: 9 x 9(VQFN)64VQFN: 81 mm2: 9 x 9(VQFN)
Power Consumption(Typ), mW1350135013501350
RatingCatalogCatalogCatalogCatalog
Reference ModeExt,IntExt,IntExt,IntExt,Int
Resolution, Bits14,16,1814,16,1814,16,1814,16,18
SFDR, dB80808080
SINAD, dB77.577.577.577.5
SNR, dB84.684.684.684.6
Sample Rate(Max), MSPS100100100100

Plan ecológico

ADS5263IRGCRADS5263IRGCR-NMADS5263IRGCTADS5263IRGCT-NM
RoHSObedienteObedienteObedienteObediente

Notas de aplicación

  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015
  • Understanding Serial LVDS Capture in High-Speed ADCs
    PDF, 1.6 Mb, Archivo publicado: jul 10, 2013
    This application note describes various schemes of interfacing serialized low-voltage differential signaling (LVDS) data outputs from high-speed analog-to-digital converters (ADCs) to a field-programmable gate arrays (FPGAs) or other application-specific integrated circuit (ASIC)-based receivers. This note provides an introduction to standard one-wire interfaces and other interface variants (such
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, Revisión: A, Archivo publicado: jul 19, 2013
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, Revisión: A, Archivo publicado: mayo 22, 2015
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015

Linea modelo

Clasificación del fabricante

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)