Datasheet Texas Instruments ADS5240 — Ficha de datos

Fabricante	Texas Instruments
Serie	ADS5240

Hojas de datos

Precios

Estado

Embalaje

Paramétricos

Parameters / Models	ADS5240IPAP	ADS5240IPAPG4	ADS5240IPAPT	ADS5240IPAPTG4
# Input Channels	4	4	4	4
Analog Input BW, MHz	300		300
Analog Input BW(MHz)		300		300
Approx. Price (US$)		32.25 | 1ku		32.25 | 1ku
Architecture	Pipeline	Pipeline	Pipeline	Pipeline
DNL(Max), +/-LSB	0.9		0.9
DNL(Max)(+/-LSB)		0.9		0.9
DNL(Typ), +/-LSB	0.4		0.4
ENOB, Bits	11.3		11.3
ENOB(Bits)		11.3		11.3
INL(Max), +/-LSB	2		2
INL(Max)(+/-LSB)		2		2
INL(Typ), +/-LSB	0.75		0.75
Input Buffer	No		No
Input Range	1	1V (p-p)	1	1V (p-p)
Interface	Parallel LVDS	Parallel LVDS	Parallel LVDS	Parallel LVDS
Operating Temperature Range, C	-40 to 85		-40 to 85
Operating Temperature Range(C)		-40 to 85		-40 to 85
Package Group	HTQFP	HTQFP	HTQFP	HTQFP
Package Size(mm2=WxL)		64HTQFP: 144 mm2: 12 x 12		64HTQFP: 144 mm2: 12 x 12
Package Size: mm2:W x L, PKG	64HTQFP: 144 mm2: 12 x 12(HTQFP)		64HTQFP: 144 mm2: 12 x 12(HTQFP)
Power Consumption(Typ), mW	607		607
Power Consumption(Typ)(mW)		607		607
Rating	Catalog	Catalog	Catalog	Catalog
Reference Mode	Ext,Int	Ext Int	Ext,Int	Ext Int
Resolution, Bits	12		12
Resolution(Bits)		12		12
SFDR, dB	85		85
SFDR(dB)		85		85
SINAD, dB	70		70
SINAD(dB)		70		70
SNR, dB	70.5		70.5
SNR(dB)		70.5		70.5
Sample Rate (max)(SPS)		40MSPS		40MSPS
Sample Rate(Max), MSPS	40		40

Plan ecológico

Notas de aplicación

• Descargar
  Interfacing High-Speed LVDS Outputs of the ADS527x/ADS524x
  PDF, 67 Kb, Archivo publicado: feb 23, 2005
  The ADS527x and ADS524x families of devices are high-performance octal/quad channel analog-to-digital converters, ideal for the highest system density. Serial low voltage differential signaling (LVDS) outputs reduce the number of I/O interfaces required, power and overall package size. These device families are rated to work from sampling rates of 20MSPS to 70MSPS, corresponding to data rates of 2
• Descargar
  CDCE62005 as Clock Solution for High-Speed ADCs
  PDF, 805 Kb, Archivo publicado: sept 4, 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
• Descargar
  Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
  PDF, 2.0 Mb, Revisión: A, Archivo publicado: mayo 22, 2015
• Descargar
  Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
  PDF, 1.2 Mb, Revisión: A, Archivo publicado: jul 19, 2013
• Descargar
  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, Archivo publicado: abr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
• Descargar
  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
• Descargar
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
• Descargar
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, Archivo publicado: jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
• Descargar
  Principles of Data Acquisition and Conversion (Rev. A)
  PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015
• Descargar
  A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
  PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
  This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
• Descargar
  Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
  PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015

Linea modelo

Clasificación del fabricante

• Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)