Datasheet Texas Instruments ADS5500MPAPEP — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | ADS5500-EP |
| Numero de parte | ADS5500MPAPEP |
Convertidor analógico a digital (ADC) de 14 bits y 125 MSPS - Producto mejorado 64-HTQFP -55 a 125
Hojas de datos
ADS5500-EP datasheet
PDF, 939 Kb, Revisión: C, Archivo publicado: sept 2, 2008
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 64 |
| Package Type | PAP |
| Industry STD Term | HTQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 160 |
| Carrier | JEDEC TRAY (10+1) |
| Device Marking | ADS5500MEP |
| Width (mm) | 10 |
| Length (mm) | 10 |
| Thickness (mm) | 1 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Descargar |
Paramétricos
| # Input Channels | 1 |
| Analog Voltage AVDD(Max) | 3.6 V |
| Analog Voltage AVDD(Min) | 3 V |
| Architecture | Pipeline |
| Digital Supply(Max) | 3.6 V |
| Digital Supply(Min) | 3 V |
| ENOB | 11.3 Bits |
| INL(Max) | 8 +/-LSB |
| Interface | Parallel CMOS |
| Operating Temperature Range | -55 to 125 C |
| Package Group | HTQFP |
| Package Size: mm2:W x L | 64HTQFP: 144 mm2: 12 x 12(HTQFP) PKG |
| Power Consumption(Typ) | 780 mW |
| Rating | HiRel Enhanced Product |
| Reference Mode | Int |
| Resolution | 14 Bits |
| SFDR | 84 dB |
| SNR | 71 dB |
| Sample Rate (max) | 125MSPS SPS |
Plan ecológico
| RoHS | Obediente |
Kits de diseño y Módulos de evaluación
- Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
Notas de aplicación
- Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC DevPDF, 627 Kb, Archivo publicado: jun 25, 2004
Texas Instruments has introduced a family of devices suited to meet the demand for high-speed, high-IF sampling ADC devices like the ADS5500 ADC, capable of sampling at 125 MSPS. To realize the full potential of these high performance devices, it is imperative to provide an extremely low phase noise clock source. The CDC7005 clock distribution chip offers a real-world clocking solution to meet the - 14-Bit, 125-MSPS ADS5500 EvaluationPDF, 738 Kb, Archivo publicado: enero 18, 2005
- Clocking High-Speed Data ConvertersPDF, 310 Kb, Archivo publicado: enero 18, 2005
- ADS5500, OPA695: PC Board Layout for Low Distortion High-Speed ADC DriversPDF, 273 Kb, Archivo publicado: abr 22, 2004
Once an analog-to-digital converter (ADC) and a driver/interface have been selected for a given application, the next step to achieving excellent performance is laying out the printed circuit board (PCB) that will support the application. This application report describes several techniques for optimizing a high-speed, 14-bit performance, differential driver PCB layout using a wideband operation - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, Archivo publicado: abr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, Archivo publicado: jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015
- Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015
Linea modelo
Serie: ADS5500-EP (4)
- ADS5500MPAPEP ADS5500MPAPREP V62/05613-01XE V62/05613-02XE
Clasificación del fabricante
- Semiconductors > Space & High Reliability > Data Converter > Analog to Digital Converters