Datasheet Texas Instruments SN74LVT125DBLE — Ficha de datos

Búfer de bus cuádruple ABT de 3.3 V con salidas de 3 estados 14-SSOP -40 a 85

Hojas de datos

PDF, 673 Kb, Revisión: F, Archivo publicado: oct 13, 2003

Extracto del documento

Estado del ciclo de vida	Obsoleto (El fabricante ha interrumpido la producción del dispositivo)
Disponibilidad de muestra del fabricante	No

Replacement	SN74LVT125DBR
Replacement Code	S

Approx. Price (US$)	0.52 \| 1ku
Bits(#)	4
F @ Nom Voltage(Max)(Mhz)	100
ICC @ Nom Voltage(Max)(mA)	0.007
Input Type	TTL/CMOS
Operating Temperature Range(C)	-40 to 85
Output Drive (IOL/IOH)(Max)(mA)	-32/64
Output Type	LVTTL
Package Group	SSOP
Package Size: mm2:W x L (PKG)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)
Rating	Catalog
Schmitt Trigger	No
Technology Family	LVT
VCC(Max)(V)	3.6
VCC(Min)(V)	2.7
Voltage(Nom)(V)	3.3
tpd @ Nom Voltage(Max)(ns)	4

RoHS	Desobediente
Pb gratis	No

Descargar
LVT Family Characteristics (Rev. A)
PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
Descargar
LVT-to-LVTH Conversion
PDF, 84 Kb, Archivo publicado: dic 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

Serie: SN74LVT125 (13)

Semiconductors > Logic > Buffer/Driver/Transceiver > Non-Inverting Buffer/Driver