Datasheet Texas Instruments CD4072BE — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | CD4072B |
| Numero de parte | CD4072BE |
CMOS Dual 4-Input OR Gate 14-PDIP -55 a 125
Hojas de datos
CD4071B, CD4072B, CD4075B TYPES datasheet
PDF, 1.7 Mb, Revisión: D, Archivo publicado: agosto 21, 2003
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 14 |
| Package Type | N |
| Industry STD Term | PDIP |
| JEDEC Code | R-PDIP-T |
| Package QTY | 25 |
| Carrier | TUBE |
| Device Marking | CD4072BE |
| Width (mm) | 6.35 |
| Length (mm) | 19.3 |
| Thickness (mm) | 3.9 |
| Pitch (mm) | 2.54 |
| Max Height (mm) | 5.08 |
| Mechanical Data | Descargar |
Paramétricos
| Bits | 2 |
| F @ Nom Voltage(Max) | 8 Mhz |
| ICC @ Nom Voltage(Max) | 0.015 mA |
| IOH(Max) | -1.5 mA |
| IOL(Max) | 1.5 mA |
| Operating Temperature Range | -55 to 125 C |
| Package Group | PDIP |
| Package Size: mm2:W x L | See datasheet (PDIP) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | CD4000 |
| VCC(Max) | 18 V |
| VCC(Min) | 3 V |
| Voltage(Nom) | 10 V |
| tpd @ Nom Voltage(Max) | 120 ns |
Plan ecológico
| RoHS | Obediente |
| Pb gratis | Sí |
Notas de aplicación
- Understanding Buffered and Unbuffered CD4xxxB Series Device CharacteristicsPDF, 188 Kb, Archivo publicado: dic 3, 2001
Both buffered and unbuffered CMOS B-series gates inverters and high-current IC products are available from TI. Each product classification has application advantages in appropriate logic-system designs. Many CMOS suppliers have concentrated on promoting buffered B-series products with applications literature focusing on the attributes and use of the buffered types. This practice has left an imb - Semiconductor Packing Material Electrostatic Discharge (ESD) ProtectionPDF, 337 Kb, Archivo publicado: jul 8, 2004
Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge - Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)PDF, 614 Kb, Revisión: C, Archivo publicado: dic 2, 2015
- Introduction to LogicPDF, 93 Kb, Archivo publicado: abr 30, 2015
Linea modelo
Serie: CD4072B (12)
Clasificación del fabricante
- Semiconductors > Logic > Gate > OR Gate