Datasheet Texas Instruments CD74AC112M96G4 — Ficha de datos

FabricanteTexas Instruments
SerieCD74AC112
Numero de parteCD74AC112M96G4
Datasheet Texas Instruments CD74AC112M96G4

Chanclas JK de doble filo de borde negativo con ajuste y reinicio 16-SOIC -55 a 125

Hojas de datos

CD54AC112, CD74AC112 datasheet
PDF, 857 Kb, Archivo publicado: enero 17, 2003
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin16
Package TypeD
Industry STD TermSOIC
JEDEC CodeR-PDSO-G
Width (mm)3.91
Length (mm)9.9
Thickness (mm)1.58
Pitch (mm)1.27
Max Height (mm)1.75
Mechanical DataDescargar

Paramétricos

Approx. Price (US$)0.19 | 1ku
Bits(#)2
F @ Nom Voltage(Max)(Mhz)100
ICC @ Nom Voltage(Max)(mA)0.04
Output Drive (IOL/IOH)(Max)(mA)-24/24
Package GroupSOIC
Package Size: mm2:W x L (PKG)See datasheet (PDIP)
RatingCatalog
Schmitt TriggerNo
Technology FamilyAC
VCC(Max)(V)5.5
VCC(Min)(V)1.5
Voltage(Nom)(V)3.3
5
tpd @ Nom Voltage(Max)(ns)11.1

Plan ecológico

RoHSDesobediente
Pb gratisNo

Notas de aplicación

  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revisión: A, Archivo publicado: feb 6, 2015
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, Archivo publicado: abr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Linea modelo

Clasificación del fabricante

  • Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop