Datasheet Texas Instruments SN74LS112ADR — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | SN74LS112A |
| Numero de parte | SN74LS112ADR |
Chanclas de doble JK de borde negativo disparado con claro y preestablecido 16-SOIC 0 a 70
Hojas de datos
Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear datasheet
PDF, 1.3 Mb, Archivo publicado: marzo 1, 1988
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 16 |
| Package Type | D |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2500 |
| Carrier | LARGE T&R |
| Device Marking | LS112A |
| Width (mm) | 3.91 |
| Length (mm) | 9.9 |
| Thickness (mm) | 1.58 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 1.75 |
| Mechanical Data | Descargar |
Paramétricos
| Bits | 2 |
| F @ Nom Voltage(Max) | 35 Mhz |
| ICC @ Nom Voltage(Max) | 6 mA |
| Output Drive (IOL/IOH)(Max) | -0.4/8 mA |
| Package Group | SOIC |
| Package Size: mm2:W x L | 16SOIC: 59 mm2: 6 x 9.9(SOIC) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | LS |
| VCC(Max) | 5.25 V |
| VCC(Min) | 4.75 V |
| Voltage(Nom) | 5 V |
| tpd @ Nom Voltage(Max) | 20 ns |
Plan ecológico
| RoHS | Obediente |
Notas de aplicación
- Designing with the SN54/74LS123 (Rev. A)PDF, 118 Kb, Revisión: A, Archivo publicado: marzo 1, 1997
The Texas Instruments (TI) SN54/74LS123 dual retriggerable monostable multivibrator is a one-shot device capable of verylong output pulses and up to 100% duty cycle. The ?LS123 also features dc triggering from gated low-level active A andhigh-level active B inputs and provides a clear input that terminates the output pulse of any predetermined time independentof timing components R ext and
Linea modelo
Serie: SN74LS112A (6)
- SN74LS112AD SN74LS112ADR SN74LS112ADRE4 SN74LS112AN SN74LS112AN3 SN74LS112ANSR
Clasificación del fabricante
- Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop