Datasheet Texas Instruments OPA3875IDBQR — Ficha de datos

OPA3875
www.ti.com . SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008 Triple 2:1 High-Speed Video Multiplexer
FEATURES DESCRIPTION 1 700MHz SMALL-SIGNAL BANDWIDTH
(AV = +2) 425MHz, 4VPP BANDWIDTH 0.1dB GAIN FLATNESS to 150MHz 4ns CHANNEL SWITCHING TIME LOW SWITCHING GLITCH: 40mVPP 3100V/Вµs SLEW RATE 0.025%/0.025В° DIFFERENTIAL GAIN, PHASE HIGH GAIN ACCURACY: 2.0V/V В±0.4% The OPA3875 offers a very wideband, 3-channel, 2:1
multiplexer in a small SSOP-16 package. Using only
11mA/ch, the OPA3875 provides three, gain of +2,
video amplifier channels with greater than 400MHz
large-signal bandwidth (4VPP). Gain accuracy and
switching glitch are improved over earlier solutions
using a new (patented) input stage switching
approach. This technique uses current steering as the
input switch while maintaining an overall closed-loop
design. Gain matching between each of the
3-channel pairs is also significantly improved using
this technique ( 100kHz 6.7 7.0 7.2 7.4 nV/√Hz max B Input Current Noise f > 100kHz 3.8 4.2 4.6 4.9 pA/√Hz max B NTSC Differential Gain RL = 150Ω 0.025 % typ C NTSC Differential Phase RL = 150Ω 0.025 C Slew Rate VO = ±2V 3100 VO = 0.5V Step Bandwidth for 0.1dB Gain Flatness SFDR ° typ V/µs min B 460 ps typ C VO = 1.4V Step 600 ps typ C Channel to Channel, RL = 150Ω ±0.05 ±0.25 ±0.3 ±0.35 % max A All inputs, RL = 150Ω ±0.1 ±0.5 ±0.6 ±0.7 % max A All three outputs ±3 ±9 ±10 ±12 mV max A All Hostile Crosstalk f = 50MHz, RL = 150Ω –50 dB typ C Channel-to-Channel Crosstalk f = 50MHz, RL = 150Ω –58 dB typ C RL = 150Ω 4 ns typ C Turn On 9 ns typ C Turn Off 60 ns typ C SEL (Channel Select) Switching Glitch All Inputs to Ground, At Matched Load 40 mVPP typ C EN (Chip-Select) Switching Glitch All Inputs to Ground, At Matched Load 15 mVPP typ C 50MHz, Chip Disabled (EN = High) –68 dB typ C Rise Time and Fall Time 2800 2700 2600 CHANNEL-TO-CHANNEL PERFORMANCE
Gain Match Output Offset Voltage Mismatch CHANNEL AND CHIP-SELECT PERFORMANCE
SEL (Channel Select) Swtiching Time
EN (Chip Select) Switching Time All Hostile Disable Feedthrough
Maximum Logic 0 EN, SEL 0.8 0.8 0.8 V max B Minimum Logic 1 EN, SEL 2.0 2.0 2.0 V min B EN Logic Input Current 0V to 4.5V 75 100 125 150 ВµA max A SEL Logic Input Current 0V to 4.5V 160 200 250 300 ВµA max A Output Offset Voltage RIN = 0Ω, G = +2V/V В±2.5 В±14 В±15.8 В±17 mV max A Average Output Offset Voltage Drift RIN = 0Ω, G = +2V/V В±50 В±50 ВµV/В°C max B В±19.5 В±20.5 ВµA max A В±40 В±40 nA/В°C max B 1.5 1.6 % max A DC PERFORMANCE Input Bias Current В±5 В±18 Average Input Bias C …