Datasheet Texas Instruments ADS8332IBRGER — Ficha de datos

FabricanteTexas Instruments
SerieADS8332
Numero de parteADS8332IBRGER
Datasheet Texas Instruments ADS8332IBRGER

ADC serial de baja potencia de 2.7V a 5.5V, 16 bits, 500KSPS con MUX de 8 canales y breakout 24-VQFN -40 a 85

Hojas de datos

ADS833x Low-Power, 16-Bit, 500-kSPS, 4- and 8-Channel Unipolar Input Analog-to-Digital Converters With Serial Interface datasheet
PDF, 1.8 Mb, Revisión: E, Archivo publicado: agosto 9, 2016
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin242424
Package TypeRGERGERGE
Industry STD TermVQFNVQFNVQFN
JEDEC CodeS-PQFP-NS-PQFP-NS-PQFP-N
Package QTY300030003000
CarrierLARGE T&RLARGE T&RLARGE T&R
Device Marking8332BADS
Width (mm)444
Length (mm)444
Thickness (mm).88.88.88
Pitch (mm).5.5.5
Max Height (mm)111
Mechanical DataDescargarDescargarDescargar

Paramétricos

# Input Channels8
Analog Voltage AVDD(Max)5.5 V
Analog Voltage AVDD(Min)2.7 V
ArchitectureSAR
Digital Supply(Max)5.5 V
Digital Supply(Min)1.65 V
INL(Max)2 +/-LSB
Input Range(Max)4.2 V
Input TypePseudo-Differential,Single-Ended
Integrated FeaturesDaisy-Chainable
InterfaceSPI
Multi-Channel ConfigurationMultiplexed
Operating Temperature Range-40 to 85 C
Package GroupVQFN
Package Size: mm2:W x L24VQFN: 16 mm2: 4 x 4(VQFN) PKG
Power Consumption(Typ)14.2 mW
RatingCatalog
Reference ModeExt
Resolution16 Bits
SINAD91 dB
SNR91.5 dB
Sample Rate (max)500kSPS SPS
Sample Rate(Max)0.5 MSPS
THD(Typ)-101 dB

Plan ecológico

RoHSObediente

Kits de diseño y Módulos de evaluación

  • Evaluation Modules & Boards: ADS8332EVMV2-PDK
    ADS8332 16-Bit 500KSPS Low-Power Serial ADC Evaluation Module Performance Demonstration Kit (PDK)
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)

Notas de aplicación

  • Interfacing the ADS8332 to the TMS320F28335 DSP
    PDF, 145 Kb, Archivo publicado: agosto 20, 2012
    ADS8332, ADS8331 Interfacing the ADS8332 to TMS320F28335 DSP LEAVE IN MS WORD
  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, Revisión: A, Archivo publicado: nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, Archivo publicado: marzo 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

Linea modelo

Clasificación del fabricante

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)