Datasheet Texas Instruments CD74AC112M96 — Ficha de datos
Fabricante | Texas Instruments |
Serie | CD74AC112 |
Numero de parte | CD74AC112M96 |
Chanclas JK de doble filo de borde negativo con ajuste y reinicio 16-SOIC -55 a 125
Hojas de datos
CD54AC112, CD74AC112 datasheet
PDF, 857 Kb, Archivo publicado: enero 17, 2003
Extracto del documento
Precios
Estado
Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
Disponibilidad de muestra del fabricante | No |
Embalaje
Pin | 16 |
Package Type | D |
Industry STD Term | SOIC |
JEDEC Code | R-PDSO-G |
Package QTY | 2500 |
Carrier | LARGE T&R |
Device Marking | AC112M |
Width (mm) | 3.91 |
Length (mm) | 9.9 |
Thickness (mm) | 1.58 |
Pitch (mm) | 1.27 |
Max Height (mm) | 1.75 |
Mechanical Data | Descargar |
Paramétricos
Bits | 2 |
F @ Nom Voltage(Max) | 100 Mhz |
ICC @ Nom Voltage(Max) | 0.04 mA |
Output Drive (IOL/IOH)(Max) | -24/24 mA |
Package Group | SOIC |
Package Size: mm2:W x L | 16SOIC: 59 mm2: 6 x 9.9(SOIC) PKG |
Rating | Catalog |
Schmitt Trigger | No |
Technology Family | AC |
VCC(Max) | 5.5 V |
VCC(Min) | 1.5 V |
Voltage(Nom) | 3.3,5 V |
tpd @ Nom Voltage(Max) | 11.1 ns |
Plan ecológico
RoHS | Obediente |
Notas de aplicación
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revisión: A, Archivo publicado: feb 6, 2015
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, Archivo publicado: abr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
Linea modelo
Serie: CD74AC112 (5)
- CD74AC112E CD74AC112EE4 CD74AC112M CD74AC112M96 CD74AC112M96G4
Clasificación del fabricante
- Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop