Datasheet Texas Instruments SN74LVTH540DBLE — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | SN74LVTH540 |
| Numero de parte | SN74LVTH540DBLE |
Búferes / controladores octales ABT de 3.3V con salidas de 3 estados 20-SSOP -40 a 85
Hojas de datos
SN54LVTH540, SN74LVTH540 datasheet
PDF, 876 Kb, Revisión: G, Archivo publicado: oct 10, 2003
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | Obsoleto (El fabricante ha interrumpido la producción del dispositivo) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 20 |
| Package Type | DB |
| Industry STD Term | SSOP |
| JEDEC Code | R-PDSO-G |
| Width (mm) | 5.3 |
| Length (mm) | 7.2 |
| Thickness (mm) | 1.95 |
| Pitch (mm) | .65 |
| Max Height (mm) | 2 |
| Mechanical Data | Descargar |
Paramétricos
| Approx. Price (US$) | 0.55 | 1ku |
| Bits(#) | 8 |
| F @ Nom Voltage(Max)(Mhz) | 160 |
| ICC @ Nom Voltage(Max)(mA) | 0.005 |
| Input Type | CMOS TTL |
| Operating Temperature Range(C) | -40 to 85 |
| Output Drive (IOL/IOH)(Max)(mA) | -32/64 |
| Output Type | CMOS |
| Package Group | SSOP |
| Package Size: mm2:W x L (PKG) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | LVT |
| VCC(Max)(V) | 3.6 |
| VCC(Min)(V) | 2.7 |
| Voltage(Nom)(V) | 3.3 |
| tpd @ Nom Voltage(Max)(ns) | 4.6 |
Plan ecológico
| RoHS | Desobediente |
| Pb gratis | No |
Notas de aplicación
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, Archivo publicado: dic 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed. - Bus-Hold CircuitPDF, 418 Kb, Archivo publicado: feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
Linea modelo
Serie: SN74LVTH540 (8)
Clasificación del fabricante
- Semiconductors > Logic > Buffer/Driver/Transceiver > Inverting Buffer/Driver