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Hojas de datosConversores analógicos a digitales - ADCTexas InstrumentsADS826
ADS826E/1K

Datasheet Texas Instruments ADS826E/1K — Ficha de datos

FabricanteTexas Instruments
SerieADS826
Numero de parteADS826E/1K
Datasheet Texas Instruments ADS826E/1K

Convertidor analógico a digital (ADC) de 10 bits y 60 MSPS 28-SSOP -40 a 85

Hojas de datos

Descargar
ADS823, ADS826: 10-Bit, 60MHz Sampling Analog-To-Digital Converter datasheet
PDF, 869 Kb, Revisión: B, Archivo publicado: jun 28, 2002
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin28
Package TypeDB
Industry STD TermSSOP
JEDEC CodeR-PDSO-G
Package QTY1000
CarrierLARGE T&R
Device MarkingADS826E
Width (mm)5.3
Length (mm)10.2
Thickness (mm)1.95
Pitch (mm).65
Max Height (mm)2
Mechanical DataDescargar

Paramétricos

# Input Channels1
Analog Input BW300 MHz
ArchitecturePipeline
DNL(Max)1 +/-LSB
DNL(Typ)0.25 +/-LSB
ENOB9.5 Bits
INL(Max)2 +/-LSB
INL(Typ)0.5 +/-LSB
Input BufferNo
Input Range1,2 Vp-p
InterfaceParallel CMOS
Operating Temperature Range-40 to 85 C
Package GroupSSOP
Package Size: mm2:W x L28SSOP: 80 mm2: 7.8 x 10.2(SSOP) PKG
Power Consumption(Typ)295 mW
RatingCatalog
Reference ModeExt,Int
Resolution10 Bits
SFDR73 dB
SINAD58 dB
SNR59 dB
Sample Rate(Max)60 MSPS

Plan ecológico

RoHSObediente

Kits de diseño y Módulos de evaluación

  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200 Low-Cost Portable Power Supply Evaluation Module
    Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)

Notas de aplicación

  • Descargar
    Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015
  • Descargar
    A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Descargar
    Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Descargar
    CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Descargar
    ADS82x ADC with non-uniform sampling clock
    PDF, 234 Kb, Archivo publicado: feb 28, 2005
  • Descargar
    RLC Filter Design for ADC Interface Applications (Rev. A)
    PDF, 299 Kb, Revisión: A, Archivo publicado: mayo 13, 2015
    As high performance Analog-to-Digital Converters (ADCs) continue to improve in their performance, the last stage interface from the final amplifier into the converter inputs becomes a critical element in the system design if the full converter dynamic range is desired. This application note describes the performance and design equations for a simple passive 2nd-order filter used successfully in AD
  • Descargar
    Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • Descargar
    Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015
  • Descargar
    CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, Archivo publicado: sept 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Descargar
    Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Archivo publicado: abr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.

Linea modelo

Serie: ADS826 (3)

Clasificación del fabricante

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)