Datasheet Texas Instruments V62/05613-01XE — Ficha de datos

Fabricante	Texas Instruments
Serie	ADS5500-EP
Numero de parte	V62/05613-01XE

Hojas de datos

Precios

Estado

Embalaje

Paramétricos

Plan ecológico

Kits de diseño y Módulos de evaluación

• Evaluation Modules & Boards: TSW2200EVM
  TSW2200 Low-Cost Portable Power Supply Evaluation Module
  Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  
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Notas de aplicación

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  14-Bit, 125-MSPS ADS5500 Evaluation
  PDF, 738 Kb, Archivo publicado: enero 18, 2005
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  Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev
  PDF, 627 Kb, Archivo publicado: jun 25, 2004
  Texas Instruments has introduced a family of devices suited to meet the demand for high-speed, high-IF sampling ADC devices like the ADS5500 ADC, capable of sampling at 125 MSPS. To realize the full potential of these high performance devices, it is imperative to provide an extremely low phase noise clock source. The CDC7005 clock distribution chip offers a real-world clocking solution to meet the
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  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
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  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, Archivo publicado: jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
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  ADS5500, OPA695: PC Board Layout for Low Distortion High-Speed ADC Drivers
  PDF, 273 Kb, Archivo publicado: abr 22, 2004
  Once an analog-to-digital converter (ADC) and a driver/interface have been selected for a given application, the next step to achieving excellent performance is laying out the printed circuit board (PCB) that will support the application. This application report describes several techniques for optimizing a high-speed, 14-bit performance, differential driver PCB layout using a wideband operation
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  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
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  Clocking High-Speed Data Converters
  PDF, 310 Kb, Archivo publicado: enero 18, 2005
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  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, Archivo publicado: abr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.

Linea modelo

Clasificación del fabricante

• Semiconductors > Space & High Reliability > Data Converter > Analog to Digital Converters

Otros nombres:

V62/0561301XE, V62/05613 01XE