Datasheet Texas Instruments THS1031IPW — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | THS1031 |
| Numero de parte | THS1031IPW |
10 bits, 30 MSPS ADC Single Ch., Integ.
Hojas de datos
3-V to 5.5-V, 10-Bit, 30 MSPS CMOS Analog-to-Digital Converter datasheet
PDF, 728 Kb, Revisión: E, Archivo publicado: marzo 21, 2002
Extracto del documento
Precios
Descripción detallada
Pinza digital de ganancia y ganancia, Indic. Fuera de rango, PowerDown 28-TSSOP -40 a 85
Estado
| Estado del ciclo de vida | Obsoleto (El fabricante ha interrumpido la producción del dispositivo) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 28 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Device Marking | TJ1031 |
| Width (mm) | 4.4 |
| Length (mm) | 9.7 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Descargar |
Reemplazos
| Replacement | ADS825E |
| Replacement Code | P |
Paramétricos
| # Input Channels | 1 |
| Analog Input BW(MHz) | 150 |
| Approx. Price (US$) | 7.67 | 100u |
| Architecture | Pipeline |
| DNL(Max)(+/-LSB) | 1 |
| ENOB(Bits) | 7.7 |
| INL(Max)(+/-LSB) | 2 |
| Input Buffer | No |
| Input Range | 2V (p-p) |
| Interface | Parallel CMOS |
| Operating Temperature Range(C) | 0 to 70 |
| Package Group | TSSOP |
| Package Size: mm2:W x L (PKG) | 28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP) |
| Power Consumption(Typ)(mW) | 160 |
| Rating | Catalog |
| Reference Mode | Ext Int |
| Resolution(Bits) | 10 |
| SFDR(dB) | 52.4 |
| SINAD(dB) | 56 |
| SNR(dB) | 49.3 |
| Sample Rate(Max)(MSPS) | 30 |
Plan ecológico
| RoHS | Desobediente |
| Pb gratis | No |
Kits de diseño y Módulos de evaluación
- Evaluation Modules & Boards: TSW2200EVM
TSW2200EVM: Low Cost Portable Power Supply
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
Notas de aplicación
- Using TI FIFOs to Interface High-Speed Data Converters With TI TMS320 DSPsPDF, 249 Kb, Archivo publicado: jun 8, 2001
Most high-speed data converters cannot be connected directly to a digital signal processor (DSP). The required transfer rates would tie up most of the DSP's I/O bandwidth. A FIFO is an appropriate solution for this problem because it can buffer a large block of data, and the DSP can read data from the FIFO in a burst mode. This is much more efficient compared to single reads for every sampled valu - CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Kb, Archivo publicado: sept 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, Archivo publicado: abr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, Archivo publicado: jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Noise Analysis for High Speed Op Amps (Rev. A)PDF, 256 Kb, Revisión: A, Archivo publicado: enero 17, 2005
As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu
Linea modelo
Serie: THS1031 (7)
Clasificación del fabricante
- Semiconductors > Data Converters > Analog to Digital Converter > High Speed ADC (>10MSPS)