Datasheet Texas Instruments ADS62C17IRGCR — Ficha de datos

Fabricante	Texas Instruments
Serie	ADS62C17
Numero de parte	ADS62C17IRGCR

Hojas de datos

Precios

Estado

Embalaje

Paramétricos

Plan ecológico

Kits de diseño y Módulos de evaluación

• Evaluation Modules & Boards: ADS62C17EVM
  ADS62C17 Dual-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter Evaluation Module
  Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  
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• Evaluation Modules & Boards: TSW2200EVM
  TSW2200 Low-Cost Portable Power Supply Evaluation Module
  Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  
  • Descargar
• Evaluation Modules & Boards: TSW1405EVM
  Data Capture: Data Converter EVMs With 8 LVDS Lanes up to 1.0Gbps
  Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
  
  • Descargar

Notas de aplicación

• Descargar
  Understanding Low-Amplitude Behavior of 11-bit ADCs
  PDF, 678 Kb, Archivo publicado: oct 22, 2011
  In TI’s line of high-speed analog-to-digital converters (ADCs) with SNRBoost technology, output amplitude tends to deviate from its expected value when the applied input amplitude is small. This application note explains this phenomenon and the reasons it occurs.
• Descargar
  QFN Layout Guidelines
  PDF, 1.3 Mb, Archivo publicado: jul 28, 2006
  Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs.
• Descargar
  CDCE62005 as Clock Solution for High-Speed ADCs
  PDF, 805 Kb, Archivo publicado: sept 4, 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
• Descargar
  Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
  PDF, 2.0 Mb, Revisión: A, Archivo publicado: mayo 22, 2015
• Descargar
  Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
  PDF, 1.2 Mb, Revisión: A, Archivo publicado: jul 19, 2013
• Descargar
  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, Archivo publicado: abr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
• Descargar
  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
• Descargar
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
• Descargar
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, Archivo publicado: jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
• Descargar
  Principles of Data Acquisition and Conversion (Rev. A)
  PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015
• Descargar
  A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
  PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
  This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
• Descargar
  Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
  PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015

Linea modelo

Clasificación del fabricante

• Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)