Datasheet Texas Instruments OMAP5912ZZG — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | OMAP5912 |
| Numero de parte | OMAP5912ZZG |
Hojas de datos
OMAP5912 Applications Processor datasheet
PDF, 2.5 Mb, Revisión: E, Archivo publicado: dic 19, 2005
Precios
Estado
| Estado del ciclo de vida | NRND (No recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 289 | 289 | 289 |
| Package Type | ZZG | ZZG | ZZG |
| Industry STD Term | BGA MICROSTAR | BGA MICROSTAR | BGA MICROSTAR |
| JEDEC Code | S-PBGA-N | S-PBGA-N | S-PBGA-N |
| Package QTY | 160 | 160 | 160 |
| Carrier | EIAJ TRAY (5+1) | EIAJ TRAY (5+1) | EIAJ TRAY (5+1) |
| Device Marking | OMAP5912ZZG | TM | OMAP |
| Width (mm) | 12 | 12 | 12 |
| Length (mm) | 12 | 12 | 12 |
| Thickness (mm) | .9 | .9 | .9 |
| Pitch (mm) | .5 | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 | 1.2 |
| Mechanical Data | Descargar | Descargar | Descargar |
Plan ecológico
| RoHS | Obediente |
Kits de diseño y Módulos de evaluación
- JTAG Emulators/ Analyzers: TMDSADP
Adaptive Clocking JTAG Emulator Adapters
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
Notas de aplicación
- DSP Instruction Cache Performance on the OMAP5912PDF, 47 Kb, Archivo publicado: feb 28, 2005
- Enabling high-speed USB OTG functionality on TI DSPsPDF, 191 Kb, Archivo publicado: mayo 18, 2007
- OMAP591x: Tuning the System Memory Requirements of DSP/BIOS LinkPDF, 251 Kb, Archivo publicado: marzo 16, 2005
The DSP/BIOSв„ў Link software has been designed to implement inter-processor communication between a host device and a DSP. For the case of OMAP591x devices, the default configuration of the DSP/BIOS Link software requires that 2MB of system memory is reserved for exclusive use by DSP/BIOS Link. The intention was to provide developers using DSP/BIOS Link plenty of memory to begin with and enab - Programming the DSP MMU in the OMAP5910 DevicePDF, 476 Kb, Archivo publicado: oct 7, 2004
The OMAP5910 device from Texas Instruments (TI) has a new dual-core architecture that is optimized for multimedia applications in a low-power environment. It couples two processorsВ—a TI-enhanced TI925T general-purpose processor and an ultralow-power TMS320C55xв„ў (C55xв„ў) digital signal processor (DSP)В—with a rich set of peripherals and powerful interfaces to achieve optimal per - Using the CSL to complement OS dispatcher in handling Cascaded InterruptsPDF, 299 Kb, Archivo publicado: nov 8, 2004
This application report discusses how CSL's INTC module could be used to share the task of dispatching interrupts with the OS, in scenarios where the OS's interrupt dispatcher does not comprehend cascaded interrupts.The solution involves having the CSL dispatch the cascaded interrupts alone, while completely leaving the job of dispatching primary CPU interrupts to the OS.We also discuss an - High-Speed Interface Layout Guidelines (Rev. G)PDF, 814 Kb, Revisión: G, Archivo publicado: jul 27, 2017
As modern bus interface frequencies scale higher, care must be taken in the printed circuit board (PCB) layout phase of a design to ensure a robust solution.
Linea modelo
Serie: OMAP5912 (3)
- OMAP5912ZDY OMAP5912ZDYA OMAP5912ZZG
Clasificación del fabricante
- Semiconductors > Processors > Other Processors