Datasheet Texas Instruments DAC5686IPZP — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | DAC5686 |
| Numero de parte | DAC5686IPZP |
Convertidor digital a analógico (DAC) de doble canal, 16 bits, 500-MSPS, 1x-16x 100-HTQFP -40 a 85
Hojas de datos
16-Bit 500 MSPS 2x-16x Interpolating Dual-Channel DAC datasheet
PDF, 861 Kb, Revisión: F, Archivo publicado: jun 3, 2009
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 100 |
| Package Type | PZP |
| Industry STD Term | HTQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 90 |
| Carrier | EIAJ TRAY (10+1) |
| Device Marking | DAC5686IPZP |
| Width (mm) | 14 |
| Length (mm) | 14 |
| Thickness (mm) | 1 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Descargar |
Paramétricos
| Architecture | Current Sink |
| DAC Channels | 2 |
| Interface | Parallel CMOS |
| Interpolation | 1x,2x,4x,8x,16x |
| Operating Temperature Range | -40 to 85 C |
| Package Group | HTQFP |
| Package Size: mm2:W x L | 100HTQFP: 256 mm2: 16 x 16(HTQFP) PKG |
| Power Consumption(Typ) | 445 mW |
| Rating | Catalog |
| Resolution | 16 Bits |
| SFDR | 72 dB |
| Sample / Update Rate | 500 MSPS |
Plan ecológico
| RoHS | Obediente |
Kits de diseño y Módulos de evaluación
- Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños) - Evaluation Modules & Boards: TSW3100EVM
TSW3100 Pattern Generator Module
Estado del ciclo de vida: Obsoleto (El fabricante ha interrumpido la producción del dispositivo)
Notas de aplicación
- DAC5686/DAC5687 Clock Generation Using PLL & External Clock Modes (Rev. A)PDF, 686 Kb, Revisión: A, Archivo publicado: jul 21, 2005
DAC5686/DAC5687 Application NOte Clock Generation Using PLL & External Clock Modes - Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACsPDF, 319 Kb, Archivo publicado: jul 14, 2009
- Passive Terminations for Current Output DACsPDF, 244 Kb, Archivo publicado: nov 10, 2008
The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance - Q3 2009 Issue Analog Applications JournalPDF, 2.1 Mb, Archivo publicado: jul 14, 2009
- High Speed Digital-to-Analog Converters Basics (Rev. A)PDF, 829 Kb, Revisión: A, Archivo publicado: oct 23, 2012
- Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, Archivo publicado: jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
Linea modelo
Serie: DAC5686 (2)
- DAC5686IPZP DAC5686IPZPG4
Clasificación del fabricante
- Semiconductors > Data Converters > Digital-to-Analog Converters (DACs) > High Speed DACs (>10MSPS)