Datasheet Texas Instruments ADS5242IPAP — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | ADS5242 |
| Numero de parte | ADS5242IPAP |
Convertidor analógico a digital de cuatro canales, 12 bits, 65-MSPS (ADC) 64-HTQFP -40 a 85
Hojas de datos
4-Channel, 12-Bit, 65MSPS Analog-to-Digital Converter with Serial LVDS Interface datasheet
PDF, 1.6 Mb, Revisión: C, Archivo publicado: oct 19, 2005
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 64 |
| Package Type | PAP |
| Industry STD Term | HTQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 160 |
| Carrier | JEDEC TRAY (10+1) |
| Device Marking | ADS5242IPAP |
| Width (mm) | 10 |
| Length (mm) | 10 |
| Thickness (mm) | 1 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Descargar |
Paramétricos
| # Input Channels | 4 |
| Analog Input BW | 300 MHz |
| Architecture | Pipeline |
| DNL(Max) | 1 +/-LSB |
| DNL(Typ) | 0.31 +/-LSB |
| ENOB | 11.5 Bits |
| INL(Max) | 2.5 +/-LSB |
| INL(Typ) | 0.41 +/-LSB |
| Input Buffer | No |
| Input Range | 2 Vp-p |
| Interface | Parallel LVDS |
| Operating Temperature Range | -40 to 85 C |
| Package Group | HTQFP |
| Package Size: mm2:W x L | 64HTQFP: 144 mm2: 12 x 12(HTQFP) PKG |
| Power Consumption(Typ) | 599 mW |
| Rating | Catalog |
| Reference Mode | Ext,Int |
| Resolution | 12 Bits |
| SFDR | 85 dB |
| SINAD | 70.8 dB |
| SNR | 71 dB |
| Sample Rate(Max) | 65 MSPS |
Plan ecológico
| RoHS | Obediente |
Kits de diseño y Módulos de evaluación
- Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
Notas de aplicación
- Interfacing High-Speed LVDS Outputs of the ADS527x/ADS524xPDF, 67 Kb, Archivo publicado: feb 23, 2005
The ADS527x and ADS524x families of devices are high-performance octal/quad channel analog-to-digital converters, ideal for the highest system density. Serial low voltage differential signaling (LVDS) outputs reduce the number of I/O interfaces required, power and overall package size. These device families are rated to work from sampling rates of 20MSPS to 70MSPS, corresponding to data rates of 2 - CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Kb, Archivo publicado: sept 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Mb, Revisión: A, Archivo publicado: mayo 22, 2015
- Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Mb, Revisión: A, Archivo publicado: jul 19, 2013
- Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, Archivo publicado: abr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, Archivo publicado: jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, Revisión: A, Archivo publicado: abr 16, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revisión: B, Archivo publicado: oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revisión: A, Archivo publicado: mayo 18, 2015
Linea modelo
Serie: ADS5242 (2)
- ADS5242IPAP ADS5242IPAPT
Clasificación del fabricante
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)