Datasheet Texas Instruments ADC10D1500CIUT — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | ADC10D1500 |
| Numero de parte | ADC10D1500CIUT |
Convertidor analógico a digital de 10 bits, doble 1.5-GSPS o simple 3.0-GSPS (ADC) 292-BGA -40 a 85
Hojas de datos
ADC10D1000/1500 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC datasheet
PDF, 2.0 Mb, Revisión: Q, Archivo publicado: marzo 15, 2013
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | NRND (No recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 292 | 292 |
| Package Type | NXA | NXA |
| Industry STD Term | BGA | BGA |
| JEDEC Code | S-PBGA-N | S-PBGA-N |
| Package QTY | 40 | 40 |
| Carrier | JEDEC TRAY (10+1) | JEDEC TRAY (10+1) |
| Device Marking | CIUT | ADC10D1500 |
| Width (mm) | 27 | 27 |
| Length (mm) | 27 | 27 |
| Thickness (mm) | 2.38 | 2.38 |
| Pitch (mm) | 1.27 | 1.27 |
| Max Height (mm) | 2.4 | 2.4 |
| Mechanical Data | Descargar | Descargar |
Reemplazos
| Replacement | ADC10D1500CIUT/NOPB |
| Replacement Code | S |
Paramétricos
| # Input Channels | 2,1 |
| Analog Input BW | 2800 MHz |
| Architecture | Folding Interpolating |
| DNL(Max) | 0.25 +/-LSB |
| DNL(Typ) | 0.25 +/-LSB |
| ENOB | 9 Bits |
| INL(Max) | 0.65 +/-LSB |
| INL(Typ) | 0.65 +/-LSB |
| Input Buffer | Yes |
| Input Range | 0.8 Vp-p |
| Interface | Parallel LVDS |
| Operating Temperature Range | -40 to 85 C |
| Package Group | BGA |
| Package Size: mm2:W x L | 292BGA: 729 mm2: 27 x 27(BGA) PKG |
| Power Consumption(Typ) | 3140 mW |
| Rating | Catalog |
| Reference Mode | Int |
| Resolution | 10 Bits |
| SFDR | 68 dB |
| SINAD | 56.1 dB |
| SNR | 56.8 dB |
| Sample Rate(Max) | 1500,3000 MSPS |
Plan ecológico
| RoHS | See ti.com |
Kits de diseño y Módulos de evaluación
- Evaluation Modules & Boards: ADC-LD-BB
ADC Low Distortion Balun Board
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños) - Evaluation Modules & Boards: ADC10D1500RB
The ADC10D1500 is a Low-Power, 10-Bit, Dual 1.5 GSPS or Single 3.0 GSPS AD Converter Reference Board
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños) - Evaluation Modules & Boards: ADC-WB-BB
ADC Wide Band Balun Board
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños) - Evaluation Modules & Boards: TC1-DESIQ-SBB
TC1 DESIQ Single Balun Board
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
Notas de aplicación
- Signal Chain Noise Figure AnalysisPDF, 615 Kb, Archivo publicado: oct 29, 2014
- AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C)PDF, 60 Kb, Revisión: C, Archivo publicado: mayo 1, 2013
In order to facilitate upgrading applications from a 10-bit Gig ADC to a 12-bit Gig ADC, the ADC10D1x00(ADC10D1500/ADC10D1000) is designed to be pin-compatible with the ADC12D1x00(ADC12D1800/1600/1000). This means that a single board layout may be designed with both resolutionADCs in mind for more cost efficient and time-to-market product development. - AN-2177 Using the LMH6554 as a ADC Driver (Rev. A)PDF, 1.7 Mb, Revisión: A, Archivo publicado: abr 26, 2013
This application report discusses the use of the Texas Instruments LMH6554 as an ADC driver. - From Sample Instant to Data Output: Understanding Latency in the GSPS ADCPDF, 392 Kb, Archivo publicado: dic 18, 2012
For many applications which use ultra high-speed ADCs, latency can be a critical performance specification. For example, if the ADC is used in any kind of feedback loop, then the absolute latency is an important factor. For a MIMO system such as a phased array radar, the relative difference and variability in latency becomes important. This application note covers latency in the GSPS ADC products, - AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G)PDF, 169 Kb, Revisión: G, Archivo publicado: feb 3, 2017
- Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of MitigatPDF, 720 Kb, Archivo publicado: dic 9, 2013
The SFDR performance of an ADC is limited by the largest spur in the spectrum from DC to Fs / 2. These spurs can either be reduced or avoided entirely for maximum SFDR performance, based on the application. This reference design explores the reason behind spurs in the 10-bit and 12-bit GSPS ADCfamily. The specific products covered are: ADC12D1800RF, ADC12D1600RF, ADC12D1000RF, ADC12D800RF, ADC12
Linea modelo
Serie: ADC10D1500 (2)
- ADC10D1500CIUT ADC10D1500CIUT/NOPB
Clasificación del fabricante
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)