Datasheet Texas Instruments TMS320C6678ACYP25 — Ficha de datos
Fabricante | Texas Instruments |
Serie | TMS320C6678 |
Numero de parte | TMS320C6678ACYP25 |
Procesador de señal digital multinúcleo fijo y de punto flotante 841-FCBGA 0 a 85
Hojas de datos
TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor datasheet
PDF, 2.2 Mb, Revisión: E, Archivo publicado: marzo 6, 2014
Extracto del documento
Precios
Estado
Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
Disponibilidad de muestra del fabricante | Sí |
Embalaje
Pin | 841 | 841 | 841 |
Package Type | CYP | CYP | CYP |
Package QTY | 44 | 44 | 44 |
Carrier | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) |
Device Marking | 1.25GHZ | TMS320C6678CYP | @2010 TI |
Width (mm) | 24 | 24 | 24 |
Length (mm) | 24 | 24 | 24 |
Thickness (mm) | 2.82 | 2.82 | 2.82 |
Mechanical Data | Descargar | Descargar | Descargar |
Paramétricos
Applications | Communications and Telecom |
DRAM | DDR3 |
DSP | 8 C66x |
DSP MHz | 1000,1250 Max. |
EMAC | 2-Port 1Gb Switch |
GFLOPS | 128,160 |
On-Chip L2 Cache | 4096 KB |
Operating Temperature Range | -40 to 100,0 to 85 C |
Other On-Chip Memory | 4096 KB |
PCI/PCIe | 2 PCIe Gen2 |
Package Size: mm2:W x L | See datasheet (FCBGA) PKG |
Rating | Catalog |
Serial I/O | I2C,RapidIO,SPI,TSIP,UART |
Serial RapidIO | 1 (four lanes) |
Total On-Chip Memory | 8832 KB |
Plan ecológico
RoHS | Obediente |
Kits de diseño y Módulos de evaluación
- Development Kits: HL5CABLE
Hyperlink Cable
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños) - Daughter Cards: TMDXEVMPCI
AMC to PCIe Adapter Card
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños) - Development Kits: TMDSEVM6678
TMS320C6678 Evaluation Modules
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños) - JTAG Emulators/ Analyzers: TMDSEMU200-U
XDS200 USB Debug Probe
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños) - JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
XDS560v2 System Trace USB & Ethernet Debug Probe
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños) - JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
XDS560v2 System Trace USB Debug Probe
Estado del ciclo de vida: Activo (Recomendado para nuevos diseños)
Notas de aplicación
- PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A)PDF, 57 Kb, Revisión: A, Archivo publicado: mayo 19, 2017
- Keystone NDK FAQPDF, 54 Kb, Archivo publicado: oct 3, 2016
This document is a collection of frequently asked questions (FAQ) on running the NDK examples on the KeyStoneв„ў family of devices. - TI Keystone DSP Hyperlink SerDes IBIS-AMI ModelsPDF, 3.2 Mb, Archivo publicado: oct 9, 2014
This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP Hyperlink interface. - TI Keystone DSP PCIe SerDes IBIS-AMI ModelsPDF, 4.8 Mb, Archivo publicado: oct 9, 2014
This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP PCIe interface. - SerDes Implementation Guidelines for KeyStone I DevicesPDF, 590 Kb, Archivo publicado: oct 31, 2012
The goal of KeyStone I SerDes collateral material is to make system implementation easier for the customer by providing the system solution. For these SerDes-based interfaces, it is not assumed that the system designer is familiar with the industry specifications, SerDes technology, or RF/microwave PCB design. However, it is still expected that the PCB design work will be supervised by a knowledge - Hardware Design Guide for KeyStone Devices (Rev. C)PDF, 1.7 Mb, Revisión: C, Archivo publicado: sept 15, 2013
- KeyStone I DDR3 Initialization (Rev. E)PDF, 114 Kb, Revisión: E, Archivo publicado: oct 28, 2016
The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP - TMS320C66x DSP Generation of Devices (Rev. A)PDF, 245 Kb, Revisión: A, Archivo publicado: abr 25, 2011
- AN-1281 Bumped Die (Flip Chip) Packages (Rev. A)PDF, 2.2 Mb, Revisión: A, Archivo publicado: mayo 1, 2004
Application Note 1281 Bumped Die (Flip Chip) Packages - SERDES Link Commissioning on KeyStone I and II DevicesPDF, 138 Kb, Archivo publicado: abr 13, 2016
The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices. - PCIe Use Cases for KeyStone DevicesPDF, 320 Kb, Archivo publicado: dic 13, 2011
- Clocking Design Guide for KeyStone DevicesPDF, 1.5 Mb, Archivo publicado: nov 9, 2010
- Optimizing Loops on the C66x DSPPDF, 585 Kb, Archivo publicado: nov 9, 2010
- The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)PDF, 20 Kb, Revisión: A, Archivo publicado: nov 10, 2010
The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM - DDR3 Design Requirements for KeyStone Devices (Rev. B)PDF, 582 Kb, Revisión: B, Archivo publicado: jun 5, 2014
- Multicore Programming Guide (Rev. B)PDF, 1.8 Mb, Revisión: B, Archivo publicado: agosto 29, 2012
As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore - Processor SDK RTOS Audio Benchmark Starter KitPDF, 530 Kb, Archivo publicado: abr 12, 2017
The TI TMS320C6000в„ў Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications that are commonly used in audio processing application. This application notes describes Audio Benchmark Starterkit software that is intended to provide an easy and quick way to benchmark key audio functions on C66x and C674x DSP device - TI DSP BenchmarkingPDF, 62 Kb, Archivo publicado: enero 13, 2016
This application report provides benchmarks for the C674x DSP core, the C66x DSP core and the ARMВ®CortexВ®-A15 core. This document also shows how to reproduce these benchmarks on specific hardware platforms. - Plastic Ball Grid Array [PBGA] Application Note (Rev. B)PDF, 1.6 Mb, Revisión: B, Archivo publicado: agosto 13, 2015
Linea modelo
Serie: TMS320C6678 (9)
Clasificación del fabricante
- Semiconductors > Processors > Digital Signal Processors > C6000 DSP > C66x DSP