Datasheet Western Design Center W65C51N6TPG-14 — Ficha de datos

October 24, 2014 W65C51N Asynchrones Communications Interface Adapter (ACIA) WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Information contained herein is provided gratuitously and without liability, to any user. Reasonable efforts have been made to verify the accuracy of the information but no guarantee whatsoever is given as to the accuracy or as to its applicability to particular uses. In every instance, it must be the responsibility of the user to determine the suitability of the products for each application. WDC products are not authorized for use as critical components in life support devices or systems. Nothing contained herein shall be construed as a recommendation to use any product in violation of existing patents or other rights of third parties. The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales Policies, copies of which are available upon request. Copyright ©1981-2014 by The Western Design Center, Inc. All rights reserved, including the right of reproduction, in whole, or in part, in any form. 2 INTRODUCTION
The WDC CMOS W65C51N Asynchronous Communications Interface Adapter (ACIA) provides an easily implemented, program controlled interface between 8-bit microprocessor based systems and serial communication data sets and modems. The ACIA has an internal baud rate generator. This feature eliminates the need for multiple component support circuits, a crystal being the only other part required. The Transmitter baud rate can be selected under program control to be either 1 of 15 different rates from 50 to 19,200 baud, or at 1/16 times an external clock rate. The Receiver baud rate may be selected under program control to be either the Transmitter rate or at 1/16 times the external clock rate. The ACIA has programmable word lengths of 5, 6, 7 or 8 bits; even, odd or no parity (Mark Parity only for Transmitter); 1, 1Ѕ or 2 bit stops. The ACIA is designed for maximum-programmed control from the microprocessor (MPU) to simplify hardware implementation. Three separate registers permit the MPU to easily select the W65C51N operating modes and data checking parameters and determine operational status. The Command Register controls parity, receiver echo mode, transmitter interrupt control, the state of the RTSB line, receiver interrupt control and the state of the DTRB line. The Control Register controls the number of stop bits, word length, and receiver clock source and baud rate. The Status Register indicates the states of the IR …