Datasheet Western Design Center W65C02S6TPLG-14 — Ficha de datos

May 17, 2013 W65C02S 8­bit Microprocessor WDC reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Information contained herein is provided gratuitously and without liability, to any user. Reasonable efforts have been made to verify the accuracy of the information but no guarantee whatsoever is given as to the accuracy or as to its applicability to particular uses. In every instance, it must be the responsibility of the user to determine the suitability of the products for each application. WDC products are not authorized for use as critical components in life support devices or systems. Nothing contained herein shall be construed as a recommendation to use any product in violation of existing patents or other rights of third parties. The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales Policies, copies of which are available upon request. Copyright 1981-2013 by The Western Design Center, Inc. reproduction, in whole, or in part, in any form. All rights reserved, including the right of TABLE OF CONTENTS
1 2 INTRODUCTION . 5
1.1 FEATURES OF THE W65C02S . 5 FUNCTIONAL DESCRIPTION . 6
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 INSTRUCTION REGISTER (IR) AND DECODE . 6 T IMING CONTROL UNIT (TCU). 6 ARITHMETIC AND L OGIC UNIT (ALU) . 6 ACCUMULATOR REGISTER (A) . 6 INDEX REGISTERS (X AND Y) . 6 PROCESSOR STATUS REGISTER (P) . 6 PROGRAM COUNTER REGISTER (PC) . 7 STACK POINTER REGISTER (S) . 7 3 PIN FUNCTION DESCRIPTION . 9
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 ADDRESS BUS (A0-A15) . 9 BUS ENABLE (BE) . 9 DATA BUS (D0-D7) . 9 INTERRUPT REQUEST (IRQB) . 9 MEMORY LOCK (MLB) . 9 NON-MASKABLE I NTERRUPT (NMIB) . 9 NO CONNECT (NC) . 9 PHASE 2 I N (PHI2), PHASE 2 O UT (PHI2O) AND PHASE 1 OUT (PHI1O) . 10 READ/WRITE (RWB) . 10 READY (RDY) . 10 RESET (RESB) . 10 SET OVERFLOW (SOB) . 11 SYNCHRONIZE WITH O PCODE FETCH (SYNC) . 11 POWER (VDD) AND GROUND (VSS) . 11 VECTOR PULL (VPB) . 11 4 ADDRESSING MODES . 15
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 ABSOLUTE A . 15 ABSOLUTE INDEXED I NDIRECT (A,X). 15 ABSOLUTE INDEXED WITH X A,X . 15 ABSOLUTE INDEXED WITH Y A, Y . 16 ABSOLUTE INDIRECT (A) . 16 ACCUMULATOR A . 16 IMMEDIATE ADDRESSING # . 16 IMPLIED I . 17 PROGRAM COUNTER RELATIVE R . 17 STACK S . 17 ZERO PAGE ZP . 17 ZERO PAGE I NDEXED I NDIRECT (ZP,X). 18 ZERO PAGE I NDEXED WITH X ZP,X . 18 ZERO PAGE I NDEXED WITH Y ZP, Y . 18 ZERO PAGE I NDIRECT (ZP) . 18 ZERO PAGE I NDIRECT INDEXED WITH Y (ZP), Y . 19 5 OPERATION TAB …